A Classification of Memory-Centric Computing

H.A. Du Nguyen, J. Yu, M.F.M. Abu Lebdeh, M. Taouil, S. Hamdioui, Francky Catthoor

Research output: Contribution to journalArticleScientificpeer-review

41 Citations (Scopus)
25 Downloads (Pure)


Technological and architectural improvements have been constantly required to sustain the demand of faster and cheaper computers. However, CMOS down-scaling is suffering from three technology walls: leakage wall, reliability wall, and cost wall. On top of that, a performance increase due to architectural improvements is also
gradually saturating due to three well-known architecture walls: memory wall, power wall, and instruction level parallelism (ILP) wall. Hence, a lot of research is focusing on proposing and developing new technologies and architectures. In this article, we present a comprehensive classification of memory-centric computing architectures; it is based on three metrics: computation location, level of parallelism, and used memory technology. The classification not only provides an overview of existing architectures with their pros and cons but also unifies the terminology that uniquely identifies these architectures and highlights the potential future architectures that can be further explored. Hence, it sets up a direction for future research in the field.
Original languageEnglish
Article number13
Pages (from-to)1-26
Number of pages26
JournalACM Journal on Emerging Technologies in Computing Systems
Issue number2
Publication statusPublished - 2020

Bibliographical note

Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.


  • Computation-in-memory
  • resistive computing
  • memory-centric computer architectures


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