A CMOS image sensor uses a column-level ADC with a multiple-ramp single-slope (MRSS) architecture. This architecture has a 3.3times shorter conversion time than classic single-slope architecture with equal power. Like the single-slope ADC, the MRSS ADC requires a single comparator per column, and, additionally, 8 switches and some digital circuitry. A prototype in a 0.25mum CMOS process has a frame rate 2.8times that of a single-slope ADC while dissipating 24% more power.
|Conference||IEEE International solid-state circuits conference, 2007, San Francisco|
|Period||11/02/07 → 15/02/07|
- conference contrib. refereed
- Conf.proc. > 3 pag