A CMOS image sensor with a column-level multiple-ramp single-slope ADC

MF Snoeij, P Donegan, AJP Theuwissen, KAA Makinwa, JH Huijsing

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

37 Citations (Scopus)


A CMOS image sensor uses a column-level ADC with a multiple-ramp single-slope (MRSS) architecture. This architecture has a 3.3times shorter conversion time than classic single-slope architecture with equal power. Like the single-slope ADC, the MRSS ADC requires a single comparator per column, and, additionally, 8 switches and some digital circuitry. A prototype in a 0.25mum CMOS process has a frame rate 2.8times that of a single-slope ADC while dissipating 24% more power.
Original languageUndefined/Unknown
Title of host publicationSolid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Editors s.n.
Place of PublicationSan Francisco, USA
Number of pages4
ISBN (Print)1-4244-0853-9
Publication statusPublished - 2007
EventIEEE International solid-state circuits conference, 2007, San Francisco - San Francisco, USA
Duration: 11 Feb 200715 Feb 2007

Publication series



ConferenceIEEE International solid-state circuits conference, 2007, San Francisco

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