Original language | English |
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Pages (from-to) | 107-118 |
Number of pages | 12 |
Journal | IEEE Transactions on Emerging Topics in Computing |
Volume | 2 |
Issue number | 2 |
DOIs | |
Publication status | Published - 2014 |
A combined design-time/test-time study of the vulnerability of sub-threshold devices to low voltage fault attacks
A Barenghi, C Hocquet, D Bol, FX Standaert, F Regazzoni, I Koren
Research output: Contribution to journal › Article › Scientific › peer-review
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