A combined design-time/test-time study of the vulnerability of sub-threshold devices to low voltage fault attacks

A Barenghi; C Hocquet; D Bol; FX Standaert; F Regazzoni; I Koren

doi:10.1109/TETC.2014.2316509

A combined design-time/test-time study of the vulnerability of sub-threshold devices to low voltage fault attacks

A Barenghi, C Hocquet, D Bol, FX Standaert, F Regazzoni, I Koren

Circuits and Systems

Research output: Contribution to journal › Article › Scientific › peer-review

12 Citations (Scopus)

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Original language	English
Pages (from-to)	107-118
Number of pages	12
Journal	IEEE Transactions on Emerging Topics in Computing
Volume	2
Issue number	2
DOIs	https://doi.org/10.1109/TETC.2014.2316509
Publication status	Published - 2014

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Harvest

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AU - Regazzoni, F

AU - Koren, I

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A combined design-time/test-time study of the vulnerability of sub-threshold devices to low voltage fault attacks

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