A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS

Chao Chieh Li, Min Shueh Yuan, Chia Chun Liao, Chih Hsien Chang, Yu Tso Lin, Tsung Hsien Tsai, Tien Chien Huang, Hsien Yuan Liao, Robert Bogdan Staszewski, More Authors

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Abstract

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm², this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL's phase detector (2.7-4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of -232dB. This topology features small area (0.034mm²), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOMT) of -247dB, and normalized TR and area (FOMTA) of -262dB.

Original languageEnglish
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
DOIs
Publication statusPublished - 2021

Keywords

  • All-digital phase-locked loop (ADPLL)
  • Clocks
  • compact area
  • Couplings
  • FinFET
  • fractional-N
  • Inductors
  • metastability
  • Oscillators
  • Phase locked loops
  • Q-factor
  • TDC gain estimator
  • time-to-digital converter (TDC)
  • transformer
  • Tuning
  • wide tuning range (TR).

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