A Cryo-CMOS PLL for Quantum Computing Applications

Research output: Contribution to journalArticleScientificpeer-review


This article presents the first cryogenic phase-locked loop (PLL) operating at 4.2 K. The PLL is designed for the control system of scalable quantum computers. The specifications of PLL are derived from the required control fidelity for a single-qubit operation. By considering the benefits and challenges of cryogenic operation, a dedicated analog PLL structure is used so as to maintain high performance from 300 to 4.2 K. The PLL incorporates a dynamic-amplifier-based charge-domain sub-sampling phase detector (PD), which simultaneously achieves low phase noise (PN) and low reference spur, thanks to its high phase-detection gain and minimized periodic disturbances on the voltage-controlled oscillator (VCO) control. Fabricated in a 40-nm CMOS process, the PLL achieves <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>78.4-dBc reference spur, 75-fs rms jitter, and 4-mW power consumption at 300 K when generating a 10-GHz carrier, leading to a <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>256.5-dB jitter-power FOM. At 4.2 K, the PLL synthesizes 9.4-to 11.6-GHz tones with an rms jitter of 37 fs and a reference spur of <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>69 dBc while consuming 2.7 mW at 10 GHz.

Original languageEnglish
Number of pages14
JournalIEEE Journal of Solid-State Circuits
Publication statusE-pub ahead of print - 2023


  • Charge-sampling
  • cryo-CMOS
  • cryo-CMOS PLL
  • dynamic amplifier
  • dynamic-amplifier-based phase detector (PD)
  • in-band phase noise (PN)
  • low jitter
  • phase-locked loop (PLL)
  • quantum computing
  • reference spur


Dive into the research topics of 'A Cryo-CMOS PLL for Quantum Computing Applications'. Together they form a unique fingerprint.

Cite this