A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing

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Abstract

This paper presents a floating inverter amplifier (FIA) that performs high-linearity amplification and sampling while driving a 2<inline-formula> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> time-interleaved (TI) SAR ADC, operating from room temperature (RT) down to 4.2 K. The power-efficient FIA samples the continuous-time input signal by windowed integration, thus avoiding the traditional sample-and-hold. Cascode switching, a floating supply and accurate pulse-width timing calibration enable high-speed operation and interleaving. In addition, by exploiting the behavior of CMOS devices at cryogenic temperatures, forward-body-biasing (FBB) is pushed well beyond what is possible at RT to ensure performance down to 4.2 K, and its impact on the performance of cryogenic circuits is analyzed. The resulting ADC, implemented in 40-nm bulk CMOS and including the FIA driver, achieves SNDR<inline-formula> <tex-math notation="LaTeX">$=$</tex-math> </inline-formula>38.7 dB (38.2 dB), SFDR<inline-formula> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula>50 dB (<inline-formula> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula>50 dB), and FOMW<inline-formula> <tex-math notation="LaTeX">$=$</tex-math> </inline-formula>25.4 fJ/conv-step (31.3 fJ/conv-step) with Nyquist-rate input at 1.0 GS/s (0.9 GS/s) at 4.2 K (RT), respectively.

Original languageEnglish
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
DOIs
Publication statusPublished - 2023

Keywords

  • ADC driver
  • cryo-CMOS
  • Cryogenics
  • FBB
  • FIA
  • forward body bias
  • Inverters
  • Linearity
  • quantum computing
  • Resistance
  • Substrates
  • Switches
  • Threshold voltage

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