TY - JOUR
T1 - A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications
AU - Homulle, Harald
AU - Visser, Stefan
AU - Charbon, Edoardo
PY - 2016/11/1
Y1 - 2016/11/1
N2 - We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmware. Therefore it can be used in a wide range of operating conditions, including a harsh cryogenic environment. The proposed architecture employs time-to-digital converters (TDCs) and phase interpolation techniques to reach a sampling rate, higher than the clock frequency (maximum 400 MHz), up to 1.2 GSa/s. The resulting FPGA ADC can achieve a 6 bit resolution (ENOB) over a 0.9 to 1.6 V input range and an effective resolution bandwidth (ERBW) of 15 MHz. This implies that the ADC has an effective Nyquist rate of 30 MHz, with an oversampling ratio of $40\times $. The system non-linearities are less than 1 LSB. The main advantages of this architecture are its scalability and reconfigurability, enabling applications with changing demands on one single platform.
AB - We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmware. Therefore it can be used in a wide range of operating conditions, including a harsh cryogenic environment. The proposed architecture employs time-to-digital converters (TDCs) and phase interpolation techniques to reach a sampling rate, higher than the clock frequency (maximum 400 MHz), up to 1.2 GSa/s. The resulting FPGA ADC can achieve a 6 bit resolution (ENOB) over a 0.9 to 1.6 V input range and an effective resolution bandwidth (ERBW) of 15 MHz. This implies that the ADC has an effective Nyquist rate of 30 MHz, with an oversampling ratio of $40\times $. The system non-linearities are less than 1 LSB. The main advantages of this architecture are its scalability and reconfigurability, enabling applications with changing demands on one single platform.
KW - ADC
KW - analog-to-digital converter
KW - calibration
KW - cryogenic
KW - FPGA
KW - reconfigurable
KW - TDC
KW - time-to-digital converter
UR - http://resolver.tudelft.nl/uuid:75e584fa-9f2d-4411-a04a-cbd685e8b418
UR - http://www.scopus.com/inward/record.url?scp=84992347216&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2016.2599927
DO - 10.1109/TCSI.2016.2599927
M3 - Article
SN - 1549-8328
VL - 63
SP - 1854
EP - 1865
JO - IEEE Transactions on Circuits and Systems Part 1: Regular Papers
JF - IEEE Transactions on Circuits and Systems Part 1: Regular Papers
IS - 11
M1 - 7593301
ER -