A-DELTA: a 64-bit high speed, compact, hybrid dynamic-CMOS/ threshold-logic adder

P Celinski, SD Cotofana, D Abbott

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

1 Citation (Scopus)
Original languageUndefined/Unknown
Title of host publicationComputational methods in neural modeling; seventh international work-conference on artificial and natural networks, IWANN 2003
EditorsJ Mira, JR Álvarez
Place of PublicationBerlin
PublisherSpringer
Pages73-80
Number of pages8
ISBN (Print)3-540-40210-1
Publication statusPublished - 2003
EventSeventh international work-conference on artificial and natural networks, Maó, Menorca - Berlin
Duration: 3 Jun 20036 Jun 2003

Publication series

Name
PublisherSpringer

Conference

ConferenceSeventh international work-conference on artificial and natural networks, Maó, Menorca
Period3/06/036/06/03

Keywords

  • Elektrotechniek
  • Techniek
  • ZX CWTS JFIS < 1.00

Cite this

Celinski, P., Cotofana, SD., & Abbott, D. (2003). A-DELTA: a 64-bit high speed, compact, hybrid dynamic-CMOS/ threshold-logic adder. In J. Mira, & JR. Álvarez (Eds.), Computational methods in neural modeling; seventh international work-conference on artificial and natural networks, IWANN 2003 (pp. 73-80). Springer.