A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS

B Wang; YH Liu; P Harpe; J van den Heuvel; B Liu; H. Gao; RB Staszewski

doi:10.1109/ISCAS.2015.7169140

A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS

B Wang, YH Liu, P Harpe, J van den Heuvel, B Liu, H. Gao, RB Staszewski

Electronics

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

11 Citations (Scopus)

Original language	English
Title of host publication	Proceedings - 2015 IEEE International Symposium on Circuits and Systems
Editors	M de Medeiras Silva
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE
Pages	2289-2292
Number of pages	4
ISBN (Print)	978-1-4799-8391-9
DOIs	https://doi.org/10.1109/ISCAS.2015.7169140
Publication status	Published - 2015
Event	IEEE ISCAS 2015: International symposium on circuits and systems - Piscataway, NJ, USA Duration: 24 May 2015 → 27 May 2015

Publication series

Name
Publisher	IEEE

Conference

Conference	IEEE ISCAS 2015
Period	24/05/15 → 27/05/15

Bibliographical note

Harvest

Access to Document

10.1109/ISCAS.2015.7169140

Cite this

Wang, B., Liu, YH., Harpe, P., van den Heuvel, J., Liu, B., Gao, H., & Staszewski, RB. (2015). A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS. In M. de Medeiras Silva (Ed.), Proceedings - 2015 IEEE International Symposium on Circuits and Systems (pp. 2289-2292). IEEE. https://doi.org/10.1109/ISCAS.2015.7169140

@inproceedings{d8186e05c7314c79814443b7192b8aba,

title = "A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS",

author = "B Wang and YH Liu and P Harpe and {van den Heuvel}, J and B Liu and H. Gao and RB Staszewski",

note = "Harvest; IEEE ISCAS 2015 : International symposium on circuits and systems ; Conference date: 24-05-2015 Through 27-05-2015",

year = "2015",

doi = "10.1109/ISCAS.2015.7169140",

language = "English",

isbn = "978-1-4799-8391-9",

publisher = "IEEE",

pages = "2289--2292",

editor = "{de Medeiras Silva}, M",

booktitle = "Proceedings - 2015 IEEE International Symposium on Circuits and Systems",

address = "United States",

}

Wang, B, Liu, YH, Harpe, P, van den Heuvel, J, Liu, B, Gao, H & Staszewski, RB 2015, A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS. in M de Medeiras Silva (ed.), Proceedings - 2015 IEEE International Symposium on Circuits and Systems. IEEE, Piscataway, NJ, USA, pp. 2289-2292, IEEE ISCAS 2015, 24/05/15. https://doi.org/10.1109/ISCAS.2015.7169140

A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS. / Wang, B; Liu, YH; Harpe, P et al.
Proceedings - 2015 IEEE International Symposium on Circuits and Systems. ed. / M de Medeiras Silva. Piscataway, NJ, USA: IEEE, 2015. p. 2289-2292.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS

AU - Wang, B

AU - Liu, YH

AU - Harpe, P

AU - van den Heuvel, J

AU - Liu, B

AU - Gao, H.

AU - Staszewski, RB

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BT - Proceedings - 2015 IEEE International Symposium on Circuits and Systems

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PB - IEEE

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T2 - IEEE ISCAS 2015

Y2 - 24 May 2015 through 27 May 2015

ER -