A Front-end ASIC with Receive Sub-Array Beamforming Integrated with a 32 x 32 PZT Matrix Transducer for 3-D Transesophageal Echocardiography

C. Chen, Z. Chen, D. Bera, S. B. Raghunathan, M. Shabanimotlagh, E. Noothout, Z. Y. Chang, C. Prins, J. G. Bosch, M. D. Verweij, N. de Jong, M. A. P. Pertijs

Research output: Contribution to journalArticleScientificpeer-review

Abstract

This paper presents a power- and area-efficient front-end application-specific integrated circuit (ASIC) that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm 2 ASIC, implemented in a low-voltage 0.18-μm CMOS process, effectively reduces the number of receive (RX) cables required in the probe's narrow shaft by ninefold with the aid of 96 delay-and-sum beamformers, each of which locally combines the signals received by a sub-array of 3 × 3 elements. These beamformers are based on pipeline-operated analog sample-and-hold stages and employ a mismatch-scrambling technique to prevent the ripple signal associated with the mismatch between these stages from limiting the dynamic range. In addition, an ultralow-power low-noise amplifier architecture is proposed to increase the power efficiency of the RX circuitry. The ASIC has a compact element matched layout and consumes only 0.27 mW/channel while receiving, which is lower than the state-of-the-art circuit. Its functionality has been successfully demonstrated in 3-D imaging experiments.
Original languageEnglish
Pages (from-to)994-1006
Number of pages13
JournalIEEE Journal of Solid State Circuits
Volume52
Issue number4
DOIs
Publication statusPublished - 2017

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