This paper presents a power- and area-efficient front-end ASIC that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable the next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm2 ASIC, implemented in a low-voltage 0.18 μm CMOS process, effectively reduces the number of cables required in the probe's narrow shaft by means of 96 sub-array beamformers, which have a compact element-matched layout and employ mismatch-scrambling to enhance the dynamic range. The ASIC consumes less than 230 mW while receiving and its functionality has been successfully demonstrated in a 3-D imaging experiment.
|Conference||30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016|
|Period||14/06/16 → 17/06/16|
- Delay lines
- Ultrasonic imaging