Abstract
This paper presents a power- and area-efficient front-end ASIC that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable the next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm2 ASIC, implemented in a low-voltage 0.18 μm CMOS process, effectively reduces the number of cables required in the probe's narrow shaft by means of 96 sub-array beamformers, which have a compact element-matched layout and employ mismatch-scrambling to enhance the dynamic range. The ASIC consumes less than 230 mW while receiving and its functionality has been successfully demonstrated in a 3-D imaging experiment.
Original language | English |
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Title of host publication | 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 |
Place of Publication | Piscataway |
Publisher | IEEE |
Pages | 1-2 |
Number of pages | 2 |
ISBN (Electronic) | 978-1-5090-0635-9 |
ISBN (Print) | 978-1-5090-0636-6 |
DOIs | |
Publication status | Published - 21 Sept 2016 |
Event | 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 - Honolulu, United States Duration: 14 Jun 2016 → 17 Jun 2016 |
Conference
Conference | 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 |
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Country/Territory | United States |
City | Honolulu |
Period | 14/06/16 → 17/06/16 |
Keywords
- Delays
- Transducers
- Delay lines
- Imaging
- Receivers
- Ultrasonic imaging
- Layout