A front-end ASIC with receive sub-array beamforming integrated with a 32 × 32 PZT matrix transducer for 3-D transesophageal echocardiography

C. Chen, Z. Chen, D. Bera, S. B. Raghunathan, M. Shabanimotlagh, E. Noothout, Z.Y. Chang, J. Ponte, C. Prins, H. J. Vos, J. G. Bosch, M. D. Verweij, N. De Jong, M. A P Pertijs

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

8 Citations (Scopus)

Abstract

This paper presents a power- and area-efficient front-end ASIC that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable the next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm2 ASIC, implemented in a low-voltage 0.18 μm CMOS process, effectively reduces the number of cables required in the probe's narrow shaft by means of 96 sub-array beamformers, which have a compact element-matched layout and employ mismatch-scrambling to enhance the dynamic range. The ASIC consumes less than 230 mW while receiving and its functionality has been successfully demonstrated in a 3-D imaging experiment.
Original languageEnglish
Title of host publication2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
Place of PublicationPiscataway
PublisherIEEE
Pages1-2
Number of pages2
ISBN (Electronic)978-1-5090-0635-9
ISBN (Print)978-1-5090-0636-6
DOIs
Publication statusPublished - 21 Sep 2016
Event30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 - Honolulu, United States
Duration: 14 Jun 201617 Jun 2016

Conference

Conference30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
CountryUnited States
CityHonolulu
Period14/06/1617/06/16

Keywords

  • Delays
  • Transducers
  • Delay lines
  • Imaging
  • Receivers
  • Ultrasonic imaging
  • Layout

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