A front-end ASIC with receive sub-array beamforming integrated with a 32 × 32 PZT matrix transducer for 3-D transesophageal echocardiography

C. Chen; Z. Chen; D. Bera; S. B. Raghunathan; M. Shabanimotlagh; E. Noothout; Z.Y. Chang; J. Ponte; C. Prins; H. J. Vos; J. G. Bosch; M. D. Verweij; N. De Jong; M. A P Pertijs

doi:10.1109/VLSIC.2016.7573470

A front-end ASIC with receive sub-array beamforming integrated with a 32 × 32 PZT matrix transducer for 3-D transesophageal echocardiography

C. Chen
, Z. Chen
, D. Bera
, S. B. Raghunathan
, M. Shabanimotlagh
, E. Noothout
, Z.Y. Chang
, J. Ponte
, C. Prins
, H. J. Vos
, J. G. Bosch
, M. D. Verweij
, N. De Jong
, M. A P Pertijs

Electronic Instrumentation

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

11 Citations (Scopus)

Abstract

This paper presents a power- and area-efficient front-end ASIC that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable the next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm2 ASIC, implemented in a low-voltage 0.18 μm CMOS process, effectively reduces the number of cables required in the probe's narrow shaft by means of 96 sub-array beamformers, which have a compact element-matched layout and employ mismatch-scrambling to enhance the dynamic range. The ASIC consumes less than 230 mW while receiving and its functionality has been successfully demonstrated in a 3-D imaging experiment.

Original language	English
Title of host publication	2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
Place of Publication	Piscataway
Publisher	IEEE
Pages	1-2
Number of pages	2
ISBN (Electronic)	978-1-5090-0635-9
ISBN (Print)	978-1-5090-0636-6
DOIs	https://doi.org/10.1109/VLSIC.2016.7573470
Publication status	Published - 21 Sept 2016
Event	30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 - Honolulu, United States Duration: 14 Jun 2016 → 17 Jun 2016

Conference

Conference	30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
Country/Territory	United States
City	Honolulu
Period	14/06/16 → 17/06/16

Keywords

Delays
Transducers
Delay lines
Imaging
Receivers
Ultrasonic imaging
Layout

Access to Document

10.1109/VLSIC.2016.7573470

Cite this

Chen, C., Chen, Z., Bera, D., Raghunathan, S. B., Shabanimotlagh, M., Noothout, E., Chang, Z. Y., Ponte, J., Prins, C., Vos, H. J., Bosch, J. G., Verweij, M. D., De Jong, N., & Pertijs, M. A. P. (2016). A front-end ASIC with receive sub-array beamforming integrated with a 32 × 32 PZT matrix transducer for 3-D transesophageal echocardiography. In 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 (pp. 1-2). Article 7573470 IEEE. https://doi.org/10.1109/VLSIC.2016.7573470

@inproceedings{d5fbe06f185f45dd806931f0fc176329,

title = "A front-end ASIC with receive sub-array beamforming integrated with a 32 × 32 PZT matrix transducer for 3-D transesophageal echocardiography",

abstract = "This paper presents a power- and area-efficient front-end ASIC that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable the next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm2 ASIC, implemented in a low-voltage 0.18 μm CMOS process, effectively reduces the number of cables required in the probe's narrow shaft by means of 96 sub-array beamformers, which have a compact element-matched layout and employ mismatch-scrambling to enhance the dynamic range. The ASIC consumes less than 230 mW while receiving and its functionality has been successfully demonstrated in a 3-D imaging experiment.",

keywords = "Delays, Transducers, Delay lines, Imaging, Receivers, Ultrasonic imaging, Layout",

author = "C. Chen and Z. Chen and D. Bera and Raghunathan, \{S. B.\} and M. Shabanimotlagh and E. Noothout and Z.Y. Chang and J. Ponte and C. Prins and Vos, \{H. J.\} and Bosch, \{J. G.\} and Verweij, \{M. D.\} and \{De Jong\}, N. and Pertijs, \{M. A P\}",

year = "2016",

month = sep,

day = "21",

doi = "10.1109/VLSIC.2016.7573470",

language = "English",

isbn = "978-1-5090-0636-6 ",

pages = "1--2",

booktitle = "2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016",

publisher = "IEEE",

address = "United States",

note = "30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 ; Conference date: 14-06-2016 Through 17-06-2016",

}

Chen, C, Chen, Z, Bera, D, Raghunathan, SB, Shabanimotlagh, M, Noothout, E , Chang, ZY, Ponte, J, Prins, C, Vos, HJ, Bosch, JG, Verweij, MD , De Jong, N & Pertijs, MAP 2016, A front-end ASIC with receive sub-array beamforming integrated with a 32 × 32 PZT matrix transducer for 3-D transesophageal echocardiography. in 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016., 7573470, IEEE, Piscataway, pp. 1-2, 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016, Honolulu, United States, 14/06/16. https://doi.org/10.1109/VLSIC.2016.7573470

A front-end ASIC with receive sub-array beamforming integrated with a 32 × 32 PZT matrix transducer for 3-D transesophageal echocardiography. / Chen, C.; Chen, Z.; Bera, D. et al.
2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016. Piscataway: IEEE, 2016. p. 1-2 7573470.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A front-end ASIC with receive sub-array beamforming integrated with a 32 × 32 PZT matrix transducer for 3-D transesophageal echocardiography

AU - Chen, C.

AU - Chen, Z.

AU - Bera, D.

AU - Raghunathan, S. B.

AU - Shabanimotlagh, M.

AU - Noothout, E.

AU - Chang, Z.Y.

AU - Ponte, J.

AU - Prins, C.

AU - Vos, H. J.

AU - Bosch, J. G.

AU - Verweij, M. D.

AU - De Jong, N.

AU - Pertijs, M. A P

PY - 2016/9/21

Y1 - 2016/9/21

N2 - This paper presents a power- and area-efficient front-end ASIC that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable the next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm2 ASIC, implemented in a low-voltage 0.18 μm CMOS process, effectively reduces the number of cables required in the probe's narrow shaft by means of 96 sub-array beamformers, which have a compact element-matched layout and employ mismatch-scrambling to enhance the dynamic range. The ASIC consumes less than 230 mW while receiving and its functionality has been successfully demonstrated in a 3-D imaging experiment.

AB - This paper presents a power- and area-efficient front-end ASIC that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable the next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm2 ASIC, implemented in a low-voltage 0.18 μm CMOS process, effectively reduces the number of cables required in the probe's narrow shaft by means of 96 sub-array beamformers, which have a compact element-matched layout and employ mismatch-scrambling to enhance the dynamic range. The ASIC consumes less than 230 mW while receiving and its functionality has been successfully demonstrated in a 3-D imaging experiment.

KW - Delays

KW - Transducers

KW - Delay lines

KW - Imaging

KW - Receivers

KW - Ultrasonic imaging

KW - Layout

U2 - 10.1109/VLSIC.2016.7573470

DO - 10.1109/VLSIC.2016.7573470

M3 - Conference contribution

AN - SCOPUS:84990990373

SN - 978-1-5090-0636-6

SP - 1

EP - 2

BT - 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016

PB - IEEE

CY - Piscataway

T2 - 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016

Y2 - 14 June 2016 through 17 June 2016

ER -

A front-end ASIC with receive sub-array beamforming integrated with a 32 × 32 PZT matrix transducer for 3-D transesophageal echocardiography

Abstract

Conference

Keywords

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