A full adder implementation using SET based linear threshold gates

CR Lageweg; SD Cotofana; S Vassiliadis

A full adder implementation using SET based linear threshold gates

CR Lageweg, SD Cotofana, S Vassiliadis

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

23 Citations (Scopus)

Original language	Undefined/Unknown
Title of host publication	Proceedings 9th IEEE International conference on electronics, circuits and systems - ICECS 2002
Editors	A Baric, et al.
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE
Pages	665-669
Number of pages	5
ISBN (Print)	0-7803-7597-1
Publication status	Published - 2002
Event	9th IEEE International Conference on Electronics, Circuits and Systems - Dubrovnik, Croatia Duration: 15 Sept 2002 → 18 Sept 2002

Publication series

Name
Publisher	IEEE

Conference

Conference	9th IEEE International Conference on Electronics, Circuits and Systems
Country/Territory	Croatia
City	Dubrovnik
Period	15/09/02 → 18/09/02

Keywords

Elektrotechniek
Techniek
conference contrib. refereed
Conf.proc. > 3 pag

Cite this

@inproceedings{b9da3f8279f347d6a95580f810d59297,

title = "A full adder implementation using SET based linear threshold gates",

keywords = "Elektrotechniek, Techniek, conference contrib. refereed, Conf.proc. > 3 pag",

author = "CR Lageweg and SD Cotofana and S Vassiliadis",

year = "2002",

language = "Undefined/Unknown",

isbn = "0-7803-7597-1",

publisher = "IEEE",

pages = "665--669",

editor = "A Baric and {et al.}",

booktitle = "Proceedings 9th IEEE International conference on electronics, circuits and systems - ICECS 2002",

address = "United States",

note = "9th IEEE International Conference on Electronics, Circuits and Systems ; Conference date: 15-09-2002 Through 18-09-2002",

}

Lageweg, CR, Cotofana, SD & Vassiliadis, S 2002, A full adder implementation using SET based linear threshold gates. in A Baric & et al. (eds), Proceedings 9th IEEE International conference on electronics, circuits and systems - ICECS 2002. IEEE, Piscataway, NJ, USA, pp. 665-669, 9th IEEE International Conference on Electronics, Circuits and Systems, Dubrovnik, Croatia, 15/09/02.

A full adder implementation using SET based linear threshold gates. / Lageweg, CR; Cotofana, SD; Vassiliadis, S.
Proceedings 9th IEEE International conference on electronics, circuits and systems - ICECS 2002. ed. / A Baric; et al. Piscataway, NJ, USA: IEEE, 2002. p. 665-669.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A full adder implementation using SET based linear threshold gates

AU - Lageweg, CR

AU - Cotofana, SD

AU - Vassiliadis, S

PY - 2002

Y1 - 2002

KW - Elektrotechniek

KW - Techniek

KW - conference contrib. refereed

KW - Conf.proc. > 3 pag

M3 - Conference contribution

SN - 0-7803-7597-1

SP - 665

EP - 669

BT - Proceedings 9th IEEE International conference on electronics, circuits and systems - ICECS 2002

A2 - Baric, A

A2 - et al., null

PB - IEEE

CY - Piscataway, NJ, USA

T2 - 9th IEEE International Conference on Electronics, Circuits and Systems

Y2 - 15 September 2002 through 18 September 2002

ER -