A Fully-Integrated Digital-Intensive Polar Doherty Transmitter

Yiyu Shen; Mohammadreza Mehrpoo; Mohsen Hashemi; Michael Polushkin; Lei Zhou; Mustafa Acar; Rene van Leuken; Morteza S. Alavi; Leo de Vreede

doi:10.1109/RFIC.2017.7969051

A Fully-Integrated Digital-Intensive Polar Doherty Transmitter

Yiyu Shen, Mohammadreza Mehrpoo, Mohsen Hashemi, Michael Polushkin, Lei Zhou, Mustafa Acar, Rene van Leuken, Morteza S. Alavi, Leo de Vreede

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

21 Citations (Scopus)

Abstract

This paper presents an advanced 2.3-2.8 GHz fully-integrated digital-intensive polar Doherty transmitter realized in 40nm standard CMOS. The proposed architecture comprises CORDIC, digital delay aligners, interpolators, digital pre-distortion (DPD) circuitry in combination with frequency-agile wideband phase modulators followed by the digital main and peak power amplifier (PA) operating in quasi-load insensitive class-E using an on-chip power combiner. At 2.5 GHz, its maximum output power is +21.4 dBm. Drain efficiency is 49.4% at peak power, and 33.7% at 6-dB power back-off. Applying DPD for a 20-MHz 64-QAM signal, the measured EVM is better than -30 dB while the average drain efficiency is 24%.

Original language	English
Title of host publication	2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
Place of Publication	Danvers, MA
Publisher	IEEE
Pages	196 - 199
Number of pages	4
ISBN (Electronic)	978-1-5090-4626-3
DOIs	https://doi.org/10.1109/RFIC.2017.7969051
Publication status	Published - 2017
Event	RFIC 2017: IEEE Radio Frequency Integrated Circuits Symposium - Hawaii Convention Center, Honolulu, HI, United States Duration: 4 Jun 2017 → 6 Jun 2017 http://rfic-ieee.org/

Conference

Conference	RFIC 2017
Country/Territory	United States
City	Honolulu, HI
Period	4/06/17 → 6/06/17
Internet address	http://rfic-ieee.org/

Bibliographical note

RMO3B-3

Keywords

Doherty transmitter
digital-intensive polar
efficiency enhancement
DPD
phase modulator
on-chip combiner

Access to Document

10.1109/RFIC.2017.7969051

http://ens.ewi.tudelft.nl/pubs/leuken17rfic.pdf

21 Citations
1 Dissertation (TU Delft)

Energy Efficient and Intrinsically Linear Digital Polar Transmitters
Hashemi, M., 2020, 182 p.
Research output: Thesis › Dissertation (TU Delft)

Open Access
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240 Downloads (Pure)

Cite this

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title = "A Fully-Integrated Digital-Intensive Polar Doherty Transmitter",

abstract = "This paper presents an advanced 2.3-2.8 GHz fully-integrated digital-intensive polar Doherty transmitter realized in 40nm standard CMOS. The proposed architecture comprises CORDIC, digital delay aligners, interpolators, digital pre-distortion (DPD) circuitry in combination with frequency-agile wideband phase modulators followed by the digital main and peak power amplifier (PA) operating in quasi-load insensitive class-E using an on-chip power combiner. At 2.5 GHz, its maximum output power is +21.4 dBm. Drain efficiency is 49.4% at peak power, and 33.7% at 6-dB power back-off. Applying DPD for a 20-MHz 64-QAM signal, the measured EVM is better than -30 dB while the average drain efficiency is 24%.",

keywords = "Doherty transmitter, digital-intensive polar, efficiency enhancement, DPD, phase modulator, on-chip combiner",

author = "Yiyu Shen and Mohammadreza Mehrpoo and Mohsen Hashemi and Michael Polushkin and Lei Zhou and Mustafa Acar and {van Leuken}, Rene and Alavi, {Morteza S.} and {de Vreede}, Leo",

note = "RMO3B-3; RFIC 2017 : IEEE Radio Frequency Integrated Circuits Symposium ; Conference date: 04-06-2017 Through 06-06-2017",

year = "2017",

doi = "10.1109/RFIC.2017.7969051",

language = "English",

pages = "196 -- 199",

booktitle = "2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)",

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AU - Shen, Yiyu

AU - Mehrpoo, Mohammadreza

AU - Hashemi, Mohsen

AU - Polushkin, Michael

AU - Zhou, Lei

AU - Acar, Mustafa

AU - van Leuken, Rene

AU - Alavi, Morteza S.

AU - de Vreede, Leo

N1 - RMO3B-3

PY - 2017

Y1 - 2017

N2 - This paper presents an advanced 2.3-2.8 GHz fully-integrated digital-intensive polar Doherty transmitter realized in 40nm standard CMOS. The proposed architecture comprises CORDIC, digital delay aligners, interpolators, digital pre-distortion (DPD) circuitry in combination with frequency-agile wideband phase modulators followed by the digital main and peak power amplifier (PA) operating in quasi-load insensitive class-E using an on-chip power combiner. At 2.5 GHz, its maximum output power is +21.4 dBm. Drain efficiency is 49.4% at peak power, and 33.7% at 6-dB power back-off. Applying DPD for a 20-MHz 64-QAM signal, the measured EVM is better than -30 dB while the average drain efficiency is 24%.

AB - This paper presents an advanced 2.3-2.8 GHz fully-integrated digital-intensive polar Doherty transmitter realized in 40nm standard CMOS. The proposed architecture comprises CORDIC, digital delay aligners, interpolators, digital pre-distortion (DPD) circuitry in combination with frequency-agile wideband phase modulators followed by the digital main and peak power amplifier (PA) operating in quasi-load insensitive class-E using an on-chip power combiner. At 2.5 GHz, its maximum output power is +21.4 dBm. Drain efficiency is 49.4% at peak power, and 33.7% at 6-dB power back-off. Applying DPD for a 20-MHz 64-QAM signal, the measured EVM is better than -30 dB while the average drain efficiency is 24%.

KW - Doherty transmitter

KW - digital-intensive polar

KW - efficiency enhancement

KW - DPD

KW - phase modulator

KW - on-chip combiner

U2 - 10.1109/RFIC.2017.7969051

DO - 10.1109/RFIC.2017.7969051

M3 - Conference contribution

SP - 196

EP - 199

BT - 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

PB - IEEE

CY - Danvers, MA

T2 - RFIC 2017

Y2 - 4 June 2017 through 6 June 2017

ER -

A Fully-Integrated Digital-Intensive Polar Doherty Transmitter

Abstract

Conference

Bibliographical note

Keywords

Access to Document

Fingerprint

Research output

Energy Efficient and Intrinsically Linear Digital Polar Transmitters

Cite this