A Fully Integrated Discrete-Time Superheterodyne Receiver

Massoud Tohidian, Iman Madadi, Robert Bogdan Staszewski

Research output: Contribution to journalArticleScientificpeer-review

19 Citations (Scopus)
387 Downloads (Pure)


The zero/low intermediate frequency (IF) receiver (RX) architecture has enabled full CMOS integration. As the technology scales and wireless standards become ever more challenging, the issues related to time-varying dc offsets, the second-order nonlinearity, and flicker noise become more critical. In this paper, we propose a new architecture of a superheterodyne RX that attempts to avoid such issues. By exploiting discrete-time (DT) operation and using only switches, capacitors, and inverter-based gm-stages as building blocks, the architecture becomes amenable to further scaling. Full integration is achieved by employing a cascade of four complex-valued passive switched-cap-based bandpass filters sampled at 4× of the local oscillator rate that perform IF image rejection. Channel selection is achieved through an equivalent of the seventh-order filtering. A new twofold noise-canceling low-noise transconductance amplifier is proposed. Frequency domain analysis of the RX is presented by the proposed DT model. The RX is wideband and covers 0.4-2.9 GHz with a noise figure of 2.9-4 dB. It is implemented in 65-nm CMOS and consumes 48-79 mW.
Original languageEnglish
Pages (from-to)635-647
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number2
Publication statusPublished - 2017


  • Bandpass filters (BPF)
  • Mixers
  • RF signals
  • Radio frequency
  • Receivers
  • Switches
  • Time-domain analysis
  • Bandpass filter (BPF)
  • IIP2
  • discrete time (DT)
  • process scalable
  • receiver (RX)
  • superheterodyne
  • switched capacitor


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