A Fully-Synchronous Offset-Insensitive Level-Crossing Analog-to-Digital Converter

Nassim Ravanshad, Hamidreza Rezaee-Dehsorkh, Reza Lotfi

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

3 Citations (Scopus)


A fully-synchronous offset-insensitive structure is proposed for implementing level-crossing analog-to-digital converters (LC-ADCs). The proposed structure is designed and implemented for high-precision compressed electrocardiogram (ECG) monitoring applications. Synchronous implementation leads to less implementation complexity compared to the conventional asynchronous implementations. Also the major source of error, viz. the difference in comparators offsets is eliminated which additionally leads to considerable saving in silicon area. Designing and simulating in a 0.18 μm CMOS technology, the LC-ADC achieves an ENOB of 8.45 bits and occupies 0.038 mm2 silicon area. The average sampling rate is about 120 S/s when applied to the whole MIT/BIH arrhythmia database. Simulation results show a power consumption of 81 nW with a 1.8 V supply voltage, by testing the ADC using Tape 100 of the MIT/BIH arrhythmia database.
Original languageEnglish
Title of host publication59th Midwest Symposium on Circuits and Systems, MWSCAS 2016
Place of PublicationPiscataway, NJ
Number of pages4
ISBN (Electronic)978-1-5090-0916-9
Publication statusPublished - 2017
Externally publishedYes
EventMWSCAS 2016: 59th IEEE International Midwest Symposium on Circuits and Systems - Khalifa University, Abu Dhabi, United Arab Emirates
Duration: 16 Oct 201619 Oct 2016


ConferenceMWSCAS 2016
CountryUnited Arab Emirates
CityAbu Dhabi
Internet address


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