Abstract
This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses the reference spurs by both minimizing the modulated capacitance seen by the voltage-controlled oscillator (VCO) tank and by reducing the duty cycle of the sampling clock. A 50μW RF-dividerless frequency-tracking loop is also introduced to lock the CSPLL robustly when the VCO faces a sudden frequency disturbance. Fabricated in a 40-nm CMOS process, the prototype CSPLL occupies a core area of 0.13 mm 2 and synthesizes 9.6-to-12-GHz tones using a 100-MHz reference. At 11.2 GHz, it achieves a reference spur of −77.3 dBc and an RMS jitter of 48.6 fs while consuming 5 mW.
Original language | English |
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Pages (from-to) | 492-504 |
Number of pages | 13 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 57 |
Issue number | 2 |
DOIs | |
Publication status | Published - 2022 |
Keywords
- Charge-sampling phase detector (CSPD)
- charge-sampling phase-locked loop (CSPLL)
- Clocks
- Detectors
- divider-less frequency-tracking loop (FTL)
- in-band phase noise (PN)
- Jitter
- low jitter
- Partial discharges
- Phase locked loops
- Radio frequency
- reference spur
- sub-sampling.
- Voltage-controlled oscillators