A Low-Noise Fractional-N Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

Zhirui Zong*, Peng Chen, Robert Bogdan Staszewski

*Corresponding author for this work

Research output: Contribution to journalArticleScientificpeer-review

21 Citations (Scopus)
122 Downloads (Pure)

Abstract

In this paper, we propose a 60-GHz fractional-N digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker (1/f 3 ) and thermal (1/f 2 ) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong third harmonic at 60 GHz which is extracted to the output while canceling the 20-GHz fundamental. The latter component is fed back to the frequency dividers in an all-digital phase-locked loop for phase detection, which comprises a pair of digital-to-time and time-to-digital converters with dithering to attenuate fractional spurs. The mechanism of flicker noise upconversion to 1/f 3 PN in the DCO is investigated, and a reduction technique is proposed. The 28-nm CMOS prototype achieves 213-277-fs rms jitter in the 57.5-67.2-GHz tuning range while consuming only 40 mW. The DCO flicker PN corner is record low at 300-400 kHz.

Original languageEnglish
Article number8594572
Pages (from-to)755-767
Number of pages13
JournalIEEE Journal of Solid-State Circuits
Volume54
Issue number3
DOIs
Publication statusPublished - 2019

Keywords

  • 60 GHz
  • All-digital phase-locked loop (ADPLL)
  • Digital-to-time converter (DTC)
  • Digitally controlled oscillator (DCO)
  • Flicker noise
  • Flicker noise upconversion
  • Fractional spur suppression
  • Fractional-N PLL
  • Harmonic boosting
  • Harmonic extraction
  • Implicit multiplier
  • Mm-wave (mmW)
  • Phase noise (PN)
  • Time-to-digital converter (TDC)

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