A low-power all-digital PLL architecture based on phase prediction

JC Zhuang; RB Staszewski

doi:10.1109/ICECS.2012.6463539

A low-power all-digital PLL architecture based on phase prediction

Electronics

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

22 Citations (Scopus)

Original language	English
Title of host publication	Proceedings 2012 19th IEEE International Conference on Electronics, Circuits and Systems
Editors	M Delgado-Restituto, M Bayoumi, A Rodríguez-Vásquez
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE Society
Pages	797-800
Number of pages	4
ISBN (Print)	1078-1-4673-1260-8
DOIs	https://doi.org/10.1109/ICECS.2012.6463539
Publication status	Published - 2012
Event	ICECS 2012, Seville, Spain - Piscataway, NJ, USA Duration: 9 Dec 2012 → 12 Dec 2012

Publication series

Name
Publisher	IEEE

Conference

Conference	ICECS 2012, Seville, Spain
Period	9/12/12 → 12/12/12

Access to Document

10.1109/ICECS.2012.6463539

Cite this

@inproceedings{9e8cdad460384f57951b27b4550f1edd,

title = "A low-power all-digital PLL architecture based on phase prediction",

author = "JC Zhuang and RB Staszewski",

year = "2012",

doi = "10.1109/ICECS.2012.6463539",

language = "English",

isbn = "1078-1-4673-1260-8",

publisher = "IEEE Society",

pages = "797--800",

editor = "M Delgado-Restituto and M Bayoumi and A Rodr{\'i}guez-V{\'a}squez",

booktitle = "Proceedings 2012 19th IEEE International Conference on Electronics, Circuits and Systems",

note = "ICECS 2012, Seville, Spain ; Conference date: 09-12-2012 Through 12-12-2012",

}

Zhuang, JC & Staszewski, RB 2012, A low-power all-digital PLL architecture based on phase prediction. in M Delgado-Restituto, M Bayoumi & A Rodríguez-Vásquez (eds), Proceedings 2012 19th IEEE International Conference on Electronics, Circuits and Systems. IEEE Society, Piscataway, NJ, USA, pp. 797-800, ICECS 2012, Seville, Spain, 9/12/12. https://doi.org/10.1109/ICECS.2012.6463539

A low-power all-digital PLL architecture based on phase prediction. / Zhuang, JC; Staszewski, RB.
Proceedings 2012 19th IEEE International Conference on Electronics, Circuits and Systems. ed. / M Delgado-Restituto; M Bayoumi; A Rodríguez-Vásquez. Piscataway, NJ, USA: IEEE Society, 2012. p. 797-800.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A low-power all-digital PLL architecture based on phase prediction

AU - Zhuang, JC

AU - Staszewski, RB

PY - 2012

Y1 - 2012

U2 - 10.1109/ICECS.2012.6463539

DO - 10.1109/ICECS.2012.6463539

M3 - Conference contribution

SN - 1078-1-4673-1260-8

SP - 797

EP - 800

BT - Proceedings 2012 19th IEEE International Conference on Electronics, Circuits and Systems

A2 - Delgado-Restituto, M

A2 - Bayoumi, M

A2 - Rodríguez-Vásquez, A

PB - IEEE Society

CY - Piscataway, NJ, USA

T2 - ICECS 2012, Seville, Spain

Y2 - 9 December 2012 through 12 December 2012

ER -