A Low-Power Oscillatory Feature Extraction Unit for Implantable Neural Interfaces

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Abstract

Power and area efficient on-chip feature extraction is needed for future closed-loop neural interfaces. This paper presents a feature extraction unit for neural oscillatory synchrony that bypasses the phase extraction step to reduce hardware complexity. Instead, the sine and cosine of the phase are directly approximated from the real and imaginary components of the signal to calculate the phase-amplitude coupling (PAC) and phase locking value (PLV). The synthesized design achieves state-of-the-art performances at 43 nW/channel and 0.006 mm2, while maintaining sufficient accuracy for seizure detection in epileptic patients.

Original languageEnglish
Title of host publicationISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings
PublisherIEEE
Number of pages5
ISBN (Electronic)9781665451093
DOIs
Publication statusPublished - 2023
Event56th IEEE International Symposium on Circuits and Systems, ISCAS 2023 - Monterey, United States
Duration: 21 May 202325 May 2023

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2023-May
ISSN (Print)0271-4310

Conference

Conference56th IEEE International Symposium on Circuits and Systems, ISCAS 2023
Country/TerritoryUnited States
CityMonterey
Period21/05/2325/05/23

Bibliographical note

Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

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