A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs&#x2014;the period of a digitally controlled oscillator (DCO) and the instantaneous time offset between the DCO and reference clock edges&#x2014;and then extracts the DCO phase error by calculating their weighted sum. The prototype, implemented in 40-nm CMOS, achieves 182-fs rms jitter with 3.5-mW power consumption. In a near-integer channel, it shows the worst fractional spur below <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>59 dBc. Under considerable supply or temperature variations, the worst spur still remains below <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>51.7 dBc without any background calibration tracking.