A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

Zhong Gao, Jingchu He, Martin Fritz, Yiyu Shen, Zhirui Zong, Gerd Spalink, Morteza S. Alavi, Robert Bogdan Staszewski, Masoud Babaie, More Authors

Research output: Contribution to journalArticleScientificpeer-review

1 Citation (Scopus)
13 Downloads (Pure)

Abstract

This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs - the period of a digitally controlled oscillator (DCO) and the instantaneous time offset between the DCO and reference clock edges - and then extracts the DCO phase error by calculating their weighted sum. The prototype, implemented in 40-nm CMOS, achieves 182-fs rms jitter with 3.5-mW power consumption. In a near-integer channel, it shows the worst fractional spur below -59 dBc. Under considerable supply or temperature variations, the worst spur still remains below -51.7 dBc without any background calibration tracking.

Original languageEnglish
Pages (from-to)1552-1571
Number of pages20
JournalIEEE Journal of Solid-State Circuits
Volume58
Issue number6
DOIs
Publication statusPublished - 2023

Keywords

  • Arithmetic
  • Capacitors
  • Clocks
  • Digital-to-time converter (DTC)
  • fractional spur
  • Microelectronics
  • Phase locked loops
  • phase-locked loop (PLL)
  • process voltage and temperature (PVT)
  • Switches
  • time-mode arithmetic unit (TAU)
  • Voltage

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