A multiported register file with register renaming for configurable softcore VLIW processors

F Anjam, JSSM Wong, MF Nadeem

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

12 Citations (Scopus)


In this paper, we present the design and implementation of a BRAM-based multiported register file with arbitrary number of read and write ports. In order to avoid the conflicts associated with write ports, we present a register renaming technique that is applied between the compiler and the assembler. This technique enables the utilization of a banked-BRAM register file as a true multiported register file. The advantage is that we do not need to modify the compiler nor the assembler and the technique is scalable. A register file with the register renaming technique has the highest performance, requires fewer resources and consumes less power compared to other approaches. As a case study, we applied our technique to the configurable open-source ρ-VEX VLIW processor. We implemented a 64 × 32-bit, 4-write and 8-read ports register file utilizing BRAMs for a 4-issue ρ-VEX processor. This register file with register renaming saves 9109 Xilinx Virtex-4 FPGA slices by just utilizing 32 BRAMs compared to a pure slice-based register file with no effect on the overall frequency of the processor as well as the cycle count for any application.
Original languageEnglish
Title of host publication2010 Intl. conf. on field programmable technology
Editors s.n.
Place of PublicationPiscataway
PublisherIEEE Society
Number of pages6
ISBN (Print)978-1-4244-8982-4
Publication statusPublished - 2010
EventFPT 2010 - Piscataway
Duration: 8 Dec 201010 Dec 2010

Publication series



ConferenceFPT 2010


  • conference contrib. refereed
  • Conf.proc. > 3 pag

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