A new methodology in power estimation in CMOS combinational circuits at logic level (U-SP-2-I-ICT)

AL Aita, LL De Oliveira, JP Dos Santos Martins

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientific

Original languageUndefined/Unknown
Title of host publicationProceedings of the 48th IEEE International Midwest Symposium On Circuits And Systems (MWSCAS2005)
Editors s.n.
Place of PublicationPiscataway
PublisherIEEE Society
Pages1127-1130
Number of pages4
ISBN (Print)0-7803-9197-7
Publication statusPublished - 2006
Event48th IEEE International Midwest Symposium On Circuits And Systems 2005, Cincinnati, USA - Piscataway
Duration: 7 Aug 200510 Aug 2005

Publication series

Name
PublisherIEEE
Name
Volume2

Conference

Conference48th IEEE International Midwest Symposium On Circuits And Systems 2005, Cincinnati, USA
Period7/08/0510/08/05

Keywords

  • professional journal papers
  • Conf.proc. > 3 pag

Cite this

Aita, AL., De Oliveira, LL., & Dos Santos Martins, JP. (2006). A new methodology in power estimation in CMOS combinational circuits at logic level (U-SP-2-I-ICT). In s.n. (Ed.), Proceedings of the 48th IEEE International Midwest Symposium On Circuits And Systems (MWSCAS2005) (pp. 1127-1130). IEEE Society.