A new methodology in power estimation in CMOS combinational circuits at logic level (U-SP-2-I-ICT)

AL Aita; LL De Oliveira; JP Dos Santos Martins

A new methodology in power estimation in CMOS combinational circuits at logic level (U-SP-2-I-ICT)

AL Aita, LL De Oliveira, JP Dos Santos Martins

Electronic Instrumentation

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific

Original language	Undefined/Unknown
Title of host publication	Proceedings of the 48th IEEE International Midwest Symposium On Circuits And Systems (MWSCAS2005)
Editors	s.n.
Place of Publication	Piscataway
Publisher	IEEE Society
Pages	1127-1130
Number of pages	4
ISBN (Print)	0-7803-9197-7
Publication status	Published - 2006
Event	48th IEEE International Midwest Symposium On Circuits And Systems 2005, Cincinnati, USA - Piscataway Duration: 7 Aug 2005 → 10 Aug 2005

Publication series

Name
Publisher	IEEE

Name
Volume	2

Conference

Conference	48th IEEE International Midwest Symposium On Circuits And Systems 2005, Cincinnati, USA
Period	7/08/05 → 10/08/05

Keywords

professional journal papers
Conf.proc. > 3 pag

Cite this

@inproceedings{710536db0b004e158212956c42047db4,

title = "A new methodology in power estimation in CMOS combinational circuits at logic level (U-SP-2-I-ICT)",

keywords = "professional journal papers, Conf.proc. > 3 pag",

author = "AL Aita and {De Oliveira}, LL and {Dos Santos Martins}, JP",

year = "2006",

language = "Undefined/Unknown",

isbn = "0-7803-9197-7",

publisher = "IEEE Society",

pages = "1127--1130",

editor = "s.n.",

booktitle = "Proceedings of the 48th IEEE International Midwest Symposium On Circuits And Systems (MWSCAS2005)",

note = "48th IEEE International Midwest Symposium On Circuits And Systems 2005, Cincinnati, USA ; Conference date: 07-08-2005 Through 10-08-2005",

}

Aita, AL, De Oliveira, LL & Dos Santos Martins, JP 2006, A new methodology in power estimation in CMOS combinational circuits at logic level (U-SP-2-I-ICT). in s.n. (ed.), Proceedings of the 48th IEEE International Midwest Symposium On Circuits And Systems (MWSCAS2005). IEEE Society, Piscataway, pp. 1127-1130, 48th IEEE International Midwest Symposium On Circuits And Systems 2005, Cincinnati, USA, 7/08/05.

A new methodology in power estimation in CMOS combinational circuits at logic level (U-SP-2-I-ICT). / Aita, AL; De Oliveira, LL; Dos Santos Martins, JP.
Proceedings of the 48th IEEE International Midwest Symposium On Circuits And Systems (MWSCAS2005). ed. / s.n. Piscataway: IEEE Society, 2006. p. 1127-1130.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific

TY - GEN

T1 - A new methodology in power estimation in CMOS combinational circuits at logic level (U-SP-2-I-ICT)

AU - Aita, AL

AU - De Oliveira, LL

AU - Dos Santos Martins, JP

PY - 2006

Y1 - 2006

KW - professional journal papers

KW - Conf.proc. > 3 pag

M3 - Conference contribution

SN - 0-7803-9197-7

SP - 1127

EP - 1130

BT - Proceedings of the 48th IEEE International Midwest Symposium On Circuits And Systems (MWSCAS2005)

A2 - s.n., null

PB - IEEE Society

CY - Piscataway

T2 - 48th IEEE International Midwest Symposium On Circuits And Systems 2005, Cincinnati, USA

Y2 - 7 August 2005 through 10 August 2005

ER -