A novel complementary push-push frequency doubler with negative resistor conversion gain enhancement

Yang Liu, Zhiqun Li, Hao Gao, Qin Li, Zhigong Wang

Research output: Contribution to journalLetterScientificpeer-review

2 Citations (Scopus)

Abstract

This letter presents a 48 GHz frequency doubler in a 65 nm CMOS technology. The proposed frequency doubler is composed of a complementary push-push structure with negative resistance circuit for conversion gain enhancement. The maximum measured conversion gain reaches −6.1 dB at 48 GHz output frequency, and the 3-dB bandwidth is 40∼54 GHz. The fundamental rejection is above 29.5 dB. The size of the proposed frequency doubler chip is 0.72 × 0.36 mm2The total power consumption is 16 mW.

Original languageEnglish
Pages (from-to)1-10
Number of pages10
JournalIEICE Electronics Express
Volume14
Issue number15
DOIs
Publication statusPublished - 1 Jan 2017

Keywords

  • CMOS
  • Complementary push-push
  • Frequency doubler
  • Negative resistor

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