A phase domain approach for mitigation of self-interference in wireless transceivers

Oren Eytan Eliezer, Robert Bogdan Staszewski, Imran Bashir, Sumeer Bhatara, Poras T. Balsara

Research output: Contribution to journalArticleScientificpeer-review

32 Citations (Scopus)


A novel approach for mitigation of self-interference in highly-integrated wireless transceivers is presented. Several examples of possible applications of this approach in a wireless cellular transceiver system-on-chip (SoC) are listed, and the application of one example is presented in detail. Mathematical analysis, simulation results, measurements, and implementation details are provided for the demonstrated technique, which was designed to minimize jitter induced onto the reference clock of a GSM transceiver's PLL. Excessive jitter on this clock, caused by multiple RF aggressors centered at harmonics of it, creates amplified in-band phase-noise at the RF output of the PLL, resulting in failures in the transmitter's performance. The identification of this highly complex interference mechanism, which represents a significant part of this work, is discussed in detail, as is the implemented solution. The presented phase-adjustment technique, leveraging specific features of the digitally intensive PLL and available digital-signal-processing resources, is demonstrated in a GSM system-on-chip (SoC) based on the Digital RF Processor (DRP) technology in 90 nm CMOS. As it does not involve dedicated hardware, nor does it noticeably increase the current consumption, it represents a cost-free solution in the final product.

Original languageEnglish
Article number4907338
Pages (from-to)1436-1453
Number of pages18
JournalIEEE Journal of Solid-State Circuits
Issue number5
Publication statusPublished - 2009
Externally publishedYes


  • All-digital PLL (ADPLL)
  • Digital RF Processor (DRP)
  • Interference mitigation
  • Jitter
  • Phase trajectory error (PTE)
  • Self-interference
  • System-on-chip (SoC)


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