A pipeline ADC for very high conversion rates

Dante Gabriel Muratore; Edoardo Bonizzoni; Franco Maloberti

doi:10.1109/ISCAS.2016.7527529

A pipeline ADC for very high conversion rates

Dante Gabriel Muratore, Edoardo Bonizzoni, Franco Maloberti

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

2 Citations (Scopus)

Abstract

This paper presents a novel pipeline configuration for wireless applications. Redundancy and multi sampling of the input techniques are used for overcoming the main limitations of pipeline ADCs. A special pre-amplifier with built-in thresholds generation is also discussed. The circuit, designed and simulated in a 65-nm CMOS technology, achieves 2.66 GS/s and 8-bit resolution. The supply voltage is 1V and the simulated power consumption is 22.06 mW, which leads to a FoM of 32.4 fJ/conversion-step.

Original language	English
Title of host publication	ISCAS 2016 - IEEE International Symposium on Circuits and Systems
Publisher	IEEE
Pages	1446-1449
Number of pages	4
ISBN (Electronic)	9781479953400
DOIs	https://doi.org/10.1109/ISCAS.2016.7527529
Publication status	Published - 2016
Externally published	Yes
Event	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016: IEEE International Symposium on Circuits and Systems - Montreal, Canada Duration: 22 May 2016 → 25 May 2016 http://iscas2016.org/

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2016-July
ISSN (Print)	0271-4310

Conference

Conference	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
Abbreviated title	ISCAS
Country/Territory	Canada
City	Montreal
Period	22/05/16 → 25/05/16
Internet address	http://iscas2016.org/

Access to Document

10.1109/ISCAS.2016.7527529

Cite this

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title = "A pipeline ADC for very high conversion rates",

abstract = "This paper presents a novel pipeline configuration for wireless applications. Redundancy and multi sampling of the input techniques are used for overcoming the main limitations of pipeline ADCs. A special pre-amplifier with built-in thresholds generation is also discussed. The circuit, designed and simulated in a 65-nm CMOS technology, achieves 2.66 GS/s and 8-bit resolution. The supply voltage is 1V and the simulated power consumption is 22.06 mW, which leads to a FoM of 32.4 fJ/conversion-step.",

author = "Muratore, {Dante Gabriel} and Edoardo Bonizzoni and Franco Maloberti",

year = "2016",

doi = "10.1109/ISCAS.2016.7527529",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "IEEE",

pages = "1446--1449",

booktitle = "ISCAS 2016 - IEEE International Symposium on Circuits and Systems",

address = "United States",

note = "2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 : IEEE International Symposium on Circuits and Systems, ISCAS ; Conference date: 22-05-2016 Through 25-05-2016",

url = "http://iscas2016.org/",

}

Muratore, DG, Bonizzoni, E & Maloberti, F 2016, A pipeline ADC for very high conversion rates. in ISCAS 2016 - IEEE International Symposium on Circuits and Systems., 7527529, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2016-July, IEEE, pp. 1446-1449, 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montreal, Canada, 22/05/16. https://doi.org/10.1109/ISCAS.2016.7527529

A pipeline ADC for very high conversion rates. / Muratore, Dante Gabriel; Bonizzoni, Edoardo; Maloberti, Franco.
ISCAS 2016 - IEEE International Symposium on Circuits and Systems. IEEE, 2016. p. 1446-1449 7527529 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2016-July).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A pipeline ADC for very high conversion rates

AU - Muratore, Dante Gabriel

AU - Bonizzoni, Edoardo

AU - Maloberti, Franco

PY - 2016

Y1 - 2016

N2 - This paper presents a novel pipeline configuration for wireless applications. Redundancy and multi sampling of the input techniques are used for overcoming the main limitations of pipeline ADCs. A special pre-amplifier with built-in thresholds generation is also discussed. The circuit, designed and simulated in a 65-nm CMOS technology, achieves 2.66 GS/s and 8-bit resolution. The supply voltage is 1V and the simulated power consumption is 22.06 mW, which leads to a FoM of 32.4 fJ/conversion-step.

AB - This paper presents a novel pipeline configuration for wireless applications. Redundancy and multi sampling of the input techniques are used for overcoming the main limitations of pipeline ADCs. A special pre-amplifier with built-in thresholds generation is also discussed. The circuit, designed and simulated in a 65-nm CMOS technology, achieves 2.66 GS/s and 8-bit resolution. The supply voltage is 1V and the simulated power consumption is 22.06 mW, which leads to a FoM of 32.4 fJ/conversion-step.

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DO - 10.1109/ISCAS.2016.7527529

M3 - Conference contribution

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T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 1446

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BT - ISCAS 2016 - IEEE International Symposium on Circuits and Systems

PB - IEEE

T2 - 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016

Y2 - 22 May 2016 through 25 May 2016

ER -

A pipeline ADC for very high conversion rates

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