A PVT-Robust Open-loop Gm-Ratio ×16 Gain Residue Amplifier for >1 GS/s Pipelined ADCs

Diogo Dias; João Goes; Tiago Costa

doi:10.1109/ISCAS58744.2024.10558154

A PVT-Robust Open-loop Gm-Ratio ×16 Gain Residue Amplifier for >1 GS/s Pipelined ADCs

Diogo Dias^*, João Goes, Tiago Costa

^*Corresponding author for this work

Bio-Electronics

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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Abstract

This work presents the design and simulation of a PVT-robust x16 gain dynamic open-loop inverter-based Gm-ratio residue-amplifier for high-speed SAR-assisted pipeline ADCs. The amplifier is designed in a 28 nm standard bulk CMOS process with a regulated 0.9 V power supply and simulated across a -20°C to 85°C temperature range. It achieves a power dissipation of 1.67 mW at 1.3 GHz, corresponding to a power-speed ratio of 1.28 mW/GHz, with less than ±5% gain variation throughout all temperature corners in typical conditions.

Original language	English
Title of host publication	ISCAS 2024 - IEEE International Symposium on Circuits and Systems
Publisher	IEEE
Number of pages	5
ISBN (Electronic)	9798350330991
DOIs	https://doi.org/10.1109/ISCAS58744.2024.10558154
Publication status	Published - 2024
Event	2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 - Singapore, Singapore Duration: 19 May 2024 → 22 May 2024

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024
Country/Territory	Singapore
City	Singapore
Period	19/05/24 → 22/05/24

Bibliographical note

Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Keywords

gm-ratio residue amplifier
pipeline analog-to-digital converter (ADC)
PVT-robust residue amplifier

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10.1109/ISCAS58744.2024.10558154

A_PVT-Robust_Open-loop_Gm-Ratio_16_Gain_Residue_Amplifier_for_gt1_GS_s_Pipelined_ADCsFinal published version, 1.59 MB

Cite this

@inproceedings{444226d4b5084d2c8c0c7e4d41a14077,

title = "A PVT-Robust Open-loop Gm-Ratio ×16 Gain Residue Amplifier for >1 GS/s Pipelined ADCs",

abstract = "This work presents the design and simulation of a PVT-robust x16 gain dynamic open-loop inverter-based Gm-ratio residue-amplifier for high-speed SAR-assisted pipeline ADCs. The amplifier is designed in a 28 nm standard bulk CMOS process with a regulated 0.9 V power supply and simulated across a -20°C to 85°C temperature range. It achieves a power dissipation of 1.67 mW at 1.3 GHz, corresponding to a power-speed ratio of 1.28 mW/GHz, with less than ±5% gain variation throughout all temperature corners in typical conditions.",

keywords = "gm-ratio residue amplifier, pipeline analog-to-digital converter (ADC), PVT-robust residue amplifier",

author = "Diogo Dias and Jo{\~a}o Goes and Tiago Costa",

note = "Green Open Access added to TU Delft Institutional Repository {\textquoteleft}You share, we take care!{\textquoteright} – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public. ; 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 ; Conference date: 19-05-2024 Through 22-05-2024",

year = "2024",

doi = "10.1109/ISCAS58744.2024.10558154",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "IEEE",

booktitle = "ISCAS 2024 - IEEE International Symposium on Circuits and Systems",

address = "United States",

}

Dias, D, Goes, J & Costa, T 2024, A PVT-Robust Open-loop Gm-Ratio ×16 Gain Residue Amplifier for >1 GS/s Pipelined ADCs. in ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Proceedings - IEEE International Symposium on Circuits and Systems, IEEE, 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024, Singapore, Singapore, 19/05/24. https://doi.org/10.1109/ISCAS58744.2024.10558154

A PVT-Robust Open-loop Gm-Ratio ×16 Gain Residue Amplifier for >1 GS/s Pipelined ADCs. / Dias, Diogo; Goes, João; Costa, Tiago.
ISCAS 2024 - IEEE International Symposium on Circuits and Systems. IEEE, 2024. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A PVT-Robust Open-loop Gm-Ratio ×16 Gain Residue Amplifier for >1 GS/s Pipelined ADCs

AU - Dias, Diogo

AU - Goes, João

AU - Costa, Tiago

N1 - Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

PY - 2024

Y1 - 2024

N2 - This work presents the design and simulation of a PVT-robust x16 gain dynamic open-loop inverter-based Gm-ratio residue-amplifier for high-speed SAR-assisted pipeline ADCs. The amplifier is designed in a 28 nm standard bulk CMOS process with a regulated 0.9 V power supply and simulated across a -20°C to 85°C temperature range. It achieves a power dissipation of 1.67 mW at 1.3 GHz, corresponding to a power-speed ratio of 1.28 mW/GHz, with less than ±5% gain variation throughout all temperature corners in typical conditions.

AB - This work presents the design and simulation of a PVT-robust x16 gain dynamic open-loop inverter-based Gm-ratio residue-amplifier for high-speed SAR-assisted pipeline ADCs. The amplifier is designed in a 28 nm standard bulk CMOS process with a regulated 0.9 V power supply and simulated across a -20°C to 85°C temperature range. It achieves a power dissipation of 1.67 mW at 1.3 GHz, corresponding to a power-speed ratio of 1.28 mW/GHz, with less than ±5% gain variation throughout all temperature corners in typical conditions.

KW - gm-ratio residue amplifier

KW - pipeline analog-to-digital converter (ADC)

KW - PVT-robust residue amplifier

UR - http://www.scopus.com/inward/record.url?scp=85198541814&partnerID=8YFLogxK

U2 - 10.1109/ISCAS58744.2024.10558154

DO - 10.1109/ISCAS58744.2024.10558154

M3 - Conference contribution

AN - SCOPUS:85198541814

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - ISCAS 2024 - IEEE International Symposium on Circuits and Systems

PB - IEEE

T2 - 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024

Y2 - 19 May 2024 through 22 May 2024

ER -

A PVT-Robust Open-loop Gm-Ratio ×16 Gain Residue Amplifier for >1 GS/s Pipelined ADCs

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