A quantitative prediction model for hardware/software partitioning

Roel Meeuws*, Yana Yankova, Koen Bertels, Georgi Gaydadjiev, Stamatis Vassiliadis

*Corresponding author for this work

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

17 Citations (Scopus)

Abstract

An important step in Heterogeneous System Development is Hardware/Software Partitioning. This process involves exploring a huge design space. By using profiling to select hot-spots and estimate area and delay we can prune the design space considerably. We present a Quantitative Model that makes early predictions to prune the design space and support the partitioning process. The model is based on Software Complexity Metrics, which capture important aspects of functions as control intensity, data intensity, and code size. To remedy interdependence among software metrics, we performed a Principal Component Analysis. The hardware characteristics were determined by automatically generating VHDL from C using the DWARV C-to-VHDL compiler. Linear regression on these data generated our model. The model error differs per hardware characteristic. We show that for flip-flops the mean error is 69%. In conclusion, our quantitative model makes fast and sufficiently accurate area predictions in support of early Hardware/Software Partitioning.

Original languageEnglish
Title of host publicationProceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL
Pages735-739
Number of pages5
DOIs
Publication statusPublished - 2007
Event2007 International Conference on Field Programmable Logic and Applications, FPL - Amsterdam, Netherlands
Duration: 27 Aug 200729 Aug 2007

Publication series

NameProceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

Conference

Conference2007 International Conference on Field Programmable Logic and Applications, FPL
Country/TerritoryNetherlands
CityAmsterdam
Period27/08/0729/08/07

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