For comprehensive understanding of how neurons communicate with each other, new tools need to be developed that can accurately mimic the behaviour of such neurons and neuron networks under `real-time' constraints. In this paper, we propose an easily customisable, highly pipelined, neuron network design, which executes optimally scheduled floating-point operations for maximal amount of biophysically plausible neurons per FPGA family type. To reduce the required amount of resources without adverse effect on the calculation latency, a single exponent instance is used for multiple neuron calculation operations. Experimental results indicate that the proposed network design allows the simulation of up to 1188 neurons on Virtex7 (XC7VX550T) device in brain real-time yielding a speed-up of x12.4 compared to the state-of-the art.
|Title of host publication||2016 IEEE 38th Annual International Conference of the Engineering in Medicine and Biology Society (EMBC)|
|Number of pages||4|
|Publication status||Published - 18 Oct 2016|
|Event||38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2016 - Orlando, Florida, United States|
Duration: 16 Aug 2016 → 20 Aug 2016
|Conference||38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2016|
|Period||16/08/16 → 20/08/16|