A scalable SIMD RISC-V based processor with customized vector extensions for CRYSTALS-kyber

Huimin Li; Nele Mentens; Stjepan Picek

doi:10.1145/3489517.3530552

A scalable SIMD RISC-V based processor with customized vector extensions for CRYSTALS-kyber

Cyber Security

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

4 Citations (Scopus)

477 Downloads (Pure)

Abstract

This paper uses RISC-V vector extensions to speed up lattice-based operations in architectures based on HW/SW co-design. We analyze the structure of the number-theoretic transform (NTT), inverse NTT (INTT), and coefficient-wise multiplication (CWM) in CRYSTALS-Kyber, a lattice-based key encapsulation mechanism. We propose 12 vector extensions for CRYSTALS-Kyber multiplication and four for finite field operations in combination with two optimizations of the HW/SW interface. This results in a speed-up of 141.7, 168.7, and 245.5 times for NTT, INTT, and CWM, respectively, compared with the baseline implementation, and a speed-up of over four times compared with the state-of-the-art HW/SW co-design using RV32IMC.

Original language	English
Title of host publication	Proceedings of the 59th ACM/IEEE Design Automation Conference, DAC 2022
Publisher	IEEE
Pages	733-738
Number of pages	6
ISBN (Electronic)	9781450391429
DOIs	https://doi.org/10.1145/3489517.3530552
Publication status	Published - 2022
Event	59th ACM/IEEE Design Automation Conference, DAC 2022 - San Francisco, United States Duration: 10 Jul 2022 → 14 Jul 2022

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

Conference

Conference	59th ACM/IEEE Design Automation Conference, DAC 2022
Country/Territory	United States
City	San Francisco
Period	10/07/22 → 14/07/22

Keywords

ISA extension
lattice-based cryptography
polynomial operation
RISC-V
SIMD processor
vector instruction

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10.1145/3489517.3530552

3489517.3530552Final published version, 1.43 MBLicence: CC BY

Cite this

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title = "A scalable SIMD RISC-V based processor with customized vector extensions for CRYSTALS-kyber",

abstract = "This paper uses RISC-V vector extensions to speed up lattice-based operations in architectures based on HW/SW co-design. We analyze the structure of the number-theoretic transform (NTT), inverse NTT (INTT), and coefficient-wise multiplication (CWM) in CRYSTALS-Kyber, a lattice-based key encapsulation mechanism. We propose 12 vector extensions for CRYSTALS-Kyber multiplication and four for finite field operations in combination with two optimizations of the HW/SW interface. This results in a speed-up of 141.7, 168.7, and 245.5 times for NTT, INTT, and CWM, respectively, compared with the baseline implementation, and a speed-up of over four times compared with the state-of-the-art HW/SW co-design using RV32IMC.",

keywords = "ISA extension, lattice-based cryptography, polynomial operation, RISC-V, SIMD processor, vector instruction",

author = "Huimin Li and Nele Mentens and Stjepan Picek",

year = "2022",

doi = "10.1145/3489517.3530552",

language = "English",

series = "Proceedings - Design Automation Conference",

publisher = "IEEE",

pages = "733--738",

booktitle = "Proceedings of the 59th ACM/IEEE Design Automation Conference, DAC 2022",

address = "United States",

note = "59th ACM/IEEE Design Automation Conference, DAC 2022 ; Conference date: 10-07-2022 Through 14-07-2022",

}

Li, H, Mentens, N & Picek, S 2022, A scalable SIMD RISC-V based processor with customized vector extensions for CRYSTALS-kyber. in Proceedings of the 59th ACM/IEEE Design Automation Conference, DAC 2022. Proceedings - Design Automation Conference, IEEE, pp. 733-738, 59th ACM/IEEE Design Automation Conference, DAC 2022, San Francisco, United States, 10/07/22. https://doi.org/10.1145/3489517.3530552

A scalable SIMD RISC-V based processor with customized vector extensions for CRYSTALS-kyber. / Li, Huimin; Mentens, Nele; Picek, Stjepan.
Proceedings of the 59th ACM/IEEE Design Automation Conference, DAC 2022. IEEE, 2022. p. 733-738 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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AU - Mentens, Nele

AU - Picek, Stjepan

PY - 2022

Y1 - 2022

N2 - This paper uses RISC-V vector extensions to speed up lattice-based operations in architectures based on HW/SW co-design. We analyze the structure of the number-theoretic transform (NTT), inverse NTT (INTT), and coefficient-wise multiplication (CWM) in CRYSTALS-Kyber, a lattice-based key encapsulation mechanism. We propose 12 vector extensions for CRYSTALS-Kyber multiplication and four for finite field operations in combination with two optimizations of the HW/SW interface. This results in a speed-up of 141.7, 168.7, and 245.5 times for NTT, INTT, and CWM, respectively, compared with the baseline implementation, and a speed-up of over four times compared with the state-of-the-art HW/SW co-design using RV32IMC.

AB - This paper uses RISC-V vector extensions to speed up lattice-based operations in architectures based on HW/SW co-design. We analyze the structure of the number-theoretic transform (NTT), inverse NTT (INTT), and coefficient-wise multiplication (CWM) in CRYSTALS-Kyber, a lattice-based key encapsulation mechanism. We propose 12 vector extensions for CRYSTALS-Kyber multiplication and four for finite field operations in combination with two optimizations of the HW/SW interface. This results in a speed-up of 141.7, 168.7, and 245.5 times for NTT, INTT, and CWM, respectively, compared with the baseline implementation, and a speed-up of over four times compared with the state-of-the-art HW/SW co-design using RV32IMC.

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A scalable SIMD RISC-V based processor with customized vector extensions for CRYSTALS-kyber

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