A scalable SIMD RISC-V based processor with customized vector extensions for CRYSTALS-kyber

Huimin Li, Nele Mentens, Stjepan Picek

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

19 Downloads (Pure)

Abstract

This paper uses RISC-V vector extensions to speed up lattice-based operations in architectures based on HW/SW co-design. We analyze the structure of the number-theoretic transform (NTT), inverse NTT (INTT), and coefficient-wise multiplication (CWM) in CRYSTALS-Kyber, a lattice-based key encapsulation mechanism. We propose 12 vector extensions for CRYSTALS-Kyber multiplication and four for finite field operations in combination with two optimizations of the HW/SW interface. This results in a speed-up of 141.7, 168.7, and 245.5 times for NTT, INTT, and CWM, respectively, compared with the baseline implementation, and a speed-up of over four times compared with the state-of-the-art HW/SW co-design using RV32IMC.

Original languageEnglish
Title of host publicationProceedings of the 59th ACM/IEEE Design Automation Conference, DAC 2022
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages733-738
Number of pages6
ISBN (Electronic)9781450391429
DOIs
Publication statusPublished - 2022
Event59th ACM/IEEE Design Automation Conference, DAC 2022 - San Francisco, United States
Duration: 10 Jul 202214 Jul 2022

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Conference

Conference59th ACM/IEEE Design Automation Conference, DAC 2022
Country/TerritoryUnited States
CitySan Francisco
Period10/07/2214/07/22

Keywords

  • ISA extension
  • lattice-based cryptography
  • polynomial operation
  • RISC-V
  • SIMD processor
  • vector instruction

Fingerprint

Dive into the research topics of 'A scalable SIMD RISC-V based processor with customized vector extensions for CRYSTALS-kyber'. Together they form a unique fingerprint.

Cite this