Abstract
In the recent years, cache based side-channel attacks have become a serious threat for computers. To face this issue, researches have been looking at verifying the security policies. However, these approaches are limited to manual security verification and they typically work for a small subset of the attacks. Hence, an effective verification environment to automatically verify the cache security for all side-channel attacks is still missing. To address this shortcoming, we propose a security verification methodology that formally verifies cache designs against cache side-channel vulnerabilities. Results show that this verification template is a straightforward, automated method in verifying cache invulnerability.
Original language | English |
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Title of host publication | 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
Subtitle of host publication | Proceedings |
Publisher | IEEE |
Pages | 1-6 |
Number of pages | 6 |
ISBN (Electronic) | 978-1-7281-9938-2 |
ISBN (Print) | 978-1-7281-9939-9 |
DOIs | |
Publication status | Published - 2020 |
Event | 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020 - Novi Sad, Serbia Duration: 22 Apr 2020 → 24 Apr 2020 |
Conference
Conference | 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020 |
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Country/Territory | Serbia |
City | Novi Sad |
Period | 22/04/20 → 24/04/20 |