A Security Verification Template to Assess Cache Architecture Vulnerabilities

Tara Ghasempouri, Jaan Raik, Kolin Paul, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

1 Citation (Scopus)
15 Downloads (Pure)

Abstract

In the recent years, cache based side-channel attacks have become a serious threat for computers. To face this issue, researches have been looking at verifying the security policies. However, these approaches are limited to manual security verification and they typically work for a small subset of the attacks. Hence, an effective verification environment to automatically verify the cache security for all side-channel attacks is still missing. To address this shortcoming, we propose a security verification methodology that formally verifies cache designs against cache side-channel vulnerabilities. Results show that this verification template is a straightforward, automated method in verifying cache invulnerability.

Original languageEnglish
Title of host publication2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Subtitle of host publicationProceedings
PublisherIEEE
Pages1-6
Number of pages6
ISBN (Electronic)978-1-7281-9938-2
ISBN (Print)978-1-7281-9939-9
DOIs
Publication statusPublished - 2020
Event23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020 - Novi Sad, Serbia
Duration: 22 Apr 202024 Apr 2020

Conference

Conference23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020
CountrySerbia
CityNovi Sad
Period22/04/2024/04/20

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