While spintronic memories, for example, spin transfer torque magnetic random access memory (STT-MRAM), have shown huge potential for building next-generation memory due to their attractive characteristics, the relatively large write latency and deficient read mechanism preclude their further application for emerging concepts, such as in-memory-processing and neuromorphic computing. A toggle spin torque (TST) MRAM combining STT and spin orbit torque (SOT) has recently been proposed to alleviate the write issue. However, the sensing featuring a good balance between the reliability and speed has not been addressed. In this paper, we propose a self-matching complementary-reference (SMCR) sensing scheme, which provides not only a maximum sensing margin (SM) but also a high-speed read operation. Through applying it in the TST-MRAM, advantageous performance in terms of both write and read processes can be realized. To validate the functionality of our proposal, we design and evaluate an 8Kb TST-MRAM array, in which a read delay of 1 ns and a read bit error rate (BER) of 1.02 × 10-13 are achieved. Moreover, when being operated at 0.8 V supply voltage, it can reduce the read access energy by 7.5% and 20%, compared with conventional voltage sensing and dynamic reference sensing schemes, respectively.
|Number of pages||12|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|Publication status||Published - 2020|
- read bit error
- sensing margin
- toggle spin torque