Abstract
Current implementations of quantum computers suffer from large numbers of control lines per qubit, becoming unmanageable with system scale up. Here, we discuss a sparse spin-qubit architecture featuring integrated control electronics significantly reducing the off-chip wire count. This quantum-classical hardware integration closes the feasibility gap towards a CMOS quantum computer.
| Original language | English |
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| Title of host publication | 2019 IEEE International Electron Devices Meeting, IEDM 2019 |
| Editors | Mariko Takayanagi |
| Publisher | IEEE |
| Number of pages | 4 |
| Volume | 2019-December |
| ISBN (Electronic) | 9781728140315 |
| DOIs | |
| Publication status | Published - 2019 |
| Event | 65th Annual IEEE International Electron Devices Meeting, IEDM 2019 - San Francisco, United States Duration: 7 Dec 2019 → 11 Dec 2019 |
Conference
| Conference | 65th Annual IEEE International Electron Devices Meeting, IEDM 2019 |
|---|---|
| Country/Territory | United States |
| City | San Francisco |
| Period | 7/12/19 → 11/12/19 |