A split transconductor high-speed SAR ADC

Dante Gabriel Muratore; Edoardo Bonizzoni; Franco Maloberti

doi:10.1109/ISCAS.2015.7169176

A split transconductor high-speed SAR ADC

Dante Gabriel Muratore, Edoardo Bonizzoni, Franco Maloberti

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

1 Citation (Scopus)

Abstract

A feasibility study of an 8-bit fast converter is presented. The advantages and limits of conventional SAR architectures are discussed and, on the basis of that, a possible optimal architecture is proposed. It uses a 4+4-bit scheme with combination of the DAC outputs in the current domain at the input of the latch. The circuit has been implemented with a 28 nm FDSOI CMOS technology. Post layout simulation results show 8bit of resolution at 1.2 GS/s.

Original language	English
Title of host publication	2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
Publisher	IEEE
Pages	2433-2436
Number of pages	4
ISBN (Electronic)	9781479983919
DOIs	https://doi.org/10.1109/ISCAS.2015.7169176
Publication status	Published - 2015
Externally published	Yes
Event	IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal Duration: 24 May 2015 → 27 May 2015

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2015-July
ISSN (Print)	0271-4310

Conference

Conference	IEEE International Symposium on Circuits and Systems, ISCAS 2015
Country/Territory	Portugal
City	Lisbon
Period	24/05/15 → 27/05/15

Access to Document

10.1109/ISCAS.2015.7169176

Cite this

@inproceedings{4fd02e05c340480f834edfedca13e036,

title = "A split transconductor high-speed SAR ADC",

abstract = "A feasibility study of an 8-bit fast converter is presented. The advantages and limits of conventional SAR architectures are discussed and, on the basis of that, a possible optimal architecture is proposed. It uses a 4+4-bit scheme with combination of the DAC outputs in the current domain at the input of the latch. The circuit has been implemented with a 28 nm FDSOI CMOS technology. Post layout simulation results show 8bit of resolution at 1.2 GS/s.",

author = "Muratore, {Dante Gabriel} and Edoardo Bonizzoni and Franco Maloberti",

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doi = "10.1109/ISCAS.2015.7169176",

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publisher = "IEEE",

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booktitle = "2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015",

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note = "IEEE International Symposium on Circuits and Systems, ISCAS 2015 ; Conference date: 24-05-2015 Through 27-05-2015",

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Muratore, DG, Bonizzoni, E & Maloberti, F 2015, A split transconductor high-speed SAR ADC. in 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015., 7169176, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2015-July, IEEE, pp. 2433-2436, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, 24/05/15. https://doi.org/10.1109/ISCAS.2015.7169176

A split transconductor high-speed SAR ADC. / Muratore, Dante Gabriel; Bonizzoni, Edoardo; Maloberti, Franco.
2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. IEEE, 2015. p. 2433-2436 7169176 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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AU - Bonizzoni, Edoardo

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N2 - A feasibility study of an 8-bit fast converter is presented. The advantages and limits of conventional SAR architectures are discussed and, on the basis of that, a possible optimal architecture is proposed. It uses a 4+4-bit scheme with combination of the DAC outputs in the current domain at the input of the latch. The circuit has been implemented with a 28 nm FDSOI CMOS technology. Post layout simulation results show 8bit of resolution at 1.2 GS/s.

AB - A feasibility study of an 8-bit fast converter is presented. The advantages and limits of conventional SAR architectures are discussed and, on the basis of that, a possible optimal architecture is proposed. It uses a 4+4-bit scheme with combination of the DAC outputs in the current domain at the input of the latch. The circuit has been implemented with a 28 nm FDSOI CMOS technology. Post layout simulation results show 8bit of resolution at 1.2 GS/s.

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T3 - Proceedings - IEEE International Symposium on Circuits and Systems

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PB - IEEE

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ER -

A split transconductor high-speed SAR ADC

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