A Supply Voltage-dependent Variation Aware Reliability Evaluation Model

Bo Yang; Emanuel Popovici; Michael Alan Quille; Andreas Amann; Sorin Cotofana

doi:10.1145/2950067.2950089

A Supply Voltage-dependent Variation Aware Reliability Evaluation Model

Bo Yang, Emanuel Popovici, Michael Alan Quille, Andreas Amann, Sorin Cotofana

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

2 Citations (Scopus)

Abstract

With the continuous scaling of CMOS VLSI technology well into the nano-meter regime, and the increasing demand for ultra low power/low voltage circuits and systems, reliability is becoming an extra design optimisation goal in addition to
size, performance, and energy. In this paper, a supply voltage Vdd-) dependent, transistor threshold voltage variation aware propagation delay estimation model and a comprehensive statistical model to evaluate the reliability of the VLSI
circuits is proposed. This accurate Vdd-dependent reliability evaluation model can be applied in the process of reliability driven multi-objective optimisation, which deals with tradeoffs between reliability, area, performance and energy. The
experimental results show that the average estimation error is within 3% when compared to Monte-Carlo SPICE simulation while saving runtime by at least 100 times for generic enchmark circuits.

Original language	English
Title of host publication	2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
Editors	W. Zhao, C.A. Moritz
Place of Publication	New York
Publisher	Association for Computing Machinery (ACM)
Pages	79-84
Number of pages	6
ISBN (Electronic)	978-1-4503-4330-5
ISBN (Print)	978-1-4673-8927-3
DOIs	https://doi.org/10.1145/2950067.2950089
Publication status	Published - 2016
Event	2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Beijing, China Duration: 18 Jul 2016 → 20 Jul 2016

Conference

Conference	2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
Abbreviated title	NANOARCH 2016
Country/Territory	China
City	Beijing
Period	18/07/16 → 20/07/16

Keywords

Statistical Timing Analysis
Delay Estimation
Delay PDF Propagation
Reliability
VLSI

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10.1145/2950067.2950089

Cite this

@inproceedings{082714ac00a64963ba0345061d16827a,

title = "A Supply Voltage-dependent Variation Aware Reliability Evaluation Model",

abstract = "With the continuous scaling of CMOS VLSI technology well into the nano-meter regime, and the increasing demand for ultra low power/low voltage circuits and systems, reliability is becoming an extra design optimisation goal in addition tosize, performance, and energy. In this paper, a supply voltage Vdd-) dependent, transistor threshold voltage variation aware propagation delay estimation model and a comprehensive statistical model to evaluate the reliability of the VLSIcircuits is proposed. This accurate Vdd-dependent reliability evaluation model can be applied in the process of reliability driven multi-objective optimisation, which deals with tradeoffs between reliability, area, performance and energy. Theexperimental results show that the average estimation error is within 3% when compared to Monte-Carlo SPICE simulation while saving runtime by at least 100 times for generic enchmark circuits.",

keywords = "Statistical Timing Analysis, Delay Estimation, Delay PDF Propagation, Reliability, VLSI",

author = "Bo Yang and Emanuel Popovici and Quille, {Michael Alan} and Andreas Amann and Sorin Cotofana",

year = "2016",

doi = "10.1145/2950067.2950089",

language = "English",

isbn = "978-1-4673-8927-3",

pages = "79--84",

editor = "W. Zhao and C.A. Moritz",

booktitle = "2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)",

publisher = "Association for Computing Machinery (ACM)",

address = "United States",

note = "2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), NANOARCH 2016 ; Conference date: 18-07-2016 Through 20-07-2016",

}

Yang, B, Popovici, E, Quille, MA, Amann, A & Cotofana, S 2016, A Supply Voltage-dependent Variation Aware Reliability Evaluation Model. in W Zhao & CA Moritz (eds), 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). Association for Computing Machinery (ACM), New York, pp. 79-84, 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Beijing, China, 18/07/16. https://doi.org/10.1145/2950067.2950089

A Supply Voltage-dependent Variation Aware Reliability Evaluation Model. / Yang, Bo; Popovici, Emanuel; Quille, Michael Alan et al.
2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). ed. / W. Zhao; C.A. Moritz. New York: Association for Computing Machinery (ACM), 2016. p. 79-84.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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T1 - A Supply Voltage-dependent Variation Aware Reliability Evaluation Model

AU - Yang, Bo

AU - Popovici, Emanuel

AU - Quille, Michael Alan

AU - Amann, Andreas

AU - Cotofana, Sorin

PY - 2016

Y1 - 2016

N2 - With the continuous scaling of CMOS VLSI technology well into the nano-meter regime, and the increasing demand for ultra low power/low voltage circuits and systems, reliability is becoming an extra design optimisation goal in addition tosize, performance, and energy. In this paper, a supply voltage Vdd-) dependent, transistor threshold voltage variation aware propagation delay estimation model and a comprehensive statistical model to evaluate the reliability of the VLSIcircuits is proposed. This accurate Vdd-dependent reliability evaluation model can be applied in the process of reliability driven multi-objective optimisation, which deals with tradeoffs between reliability, area, performance and energy. Theexperimental results show that the average estimation error is within 3% when compared to Monte-Carlo SPICE simulation while saving runtime by at least 100 times for generic enchmark circuits.

AB - With the continuous scaling of CMOS VLSI technology well into the nano-meter regime, and the increasing demand for ultra low power/low voltage circuits and systems, reliability is becoming an extra design optimisation goal in addition tosize, performance, and energy. In this paper, a supply voltage Vdd-) dependent, transistor threshold voltage variation aware propagation delay estimation model and a comprehensive statistical model to evaluate the reliability of the VLSIcircuits is proposed. This accurate Vdd-dependent reliability evaluation model can be applied in the process of reliability driven multi-objective optimisation, which deals with tradeoffs between reliability, area, performance and energy. Theexperimental results show that the average estimation error is within 3% when compared to Monte-Carlo SPICE simulation while saving runtime by at least 100 times for generic enchmark circuits.

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KW - Delay Estimation

KW - Delay PDF Propagation

KW - Reliability

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DO - 10.1145/2950067.2950089

M3 - Conference contribution

SN - 978-1-4673-8927-3

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A2 - Moritz, C.A.

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ER -

A Supply Voltage-dependent Variation Aware Reliability Evaluation Model

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Keywords

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