A Survey and Evaluation of FPGA High-Level Synthesis Tools

R Nane, VM Sima, Christian Pilato, J Choi, B Fort, A Canis, YT Chen, H Hsiao, S Brown, F Ferrandi, J Anderson, K Bertels

Research output: Contribution to journalArticleScientificpeer-review

347 Citations (Scopus)


High-level synthesis (HLS) is increasingly popular for the design of high-performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today’s system complexity. HLS allows designers to work at a higherlevel of abstraction by using a software program to specify the
hardware functionality. Additionally, HLS is particularly interesting for designing field-programmable gate array circuits, where hardware implementations can be easily refined and replaced in the target device. Recent years have seen much activity in the HLS research community, with a plethora of HLS tool offerings,
from both industry and academia. All these tools may have different input languages, perform different internal optimizations, and produce results of different quality, even for the very same input description. Hence, it is challenging to compare their performance and understand which is the best for the hardware to be implemented. We present a comprehensive analysis
of recent HLS tools, as well as overview the areas of active interest in the HLS research community. We also present a firstpublished methodology to evaluate different HLS tools. We use our methodology to compare one commercial and three academic tools on a common set of C benchmarks, aiming at performing
an in-depth evaluation in terms of performance and the use of resources.
Original languageEnglish
Pages (from-to)1591-1604
Number of pages14
JournalIEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems
Issue number10
Publication statusPublished - 2016


Dive into the research topics of 'A Survey and Evaluation of FPGA High-Level Synthesis Tools'. Together they form a unique fingerprint.

Cite this