A Versatile and Efficient 0.1-to-11 Gb/s CML Transmitter in 40-nm CMOS

Jun Feng; Mohammadreza  Beikmirza; Mohammadreza Mehrpoo; Leo C.N. de Vreede; Morteza S.  Alavi

doi:10.1109/ISOCC53507.2021.9613887

A Versatile and Efficient 0.1-to-11 Gb/s CML Transmitter in 40-nm CMOS

Jun Feng, Mohammadreza Beikmirza, Mohammadreza Mehrpoo, Leo C.N. de Vreede, Morteza S. Alavi

Electronics

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

142 Downloads (Pure)

Abstract

We present a wireline transmitter (TX) for re-configurable chip-to-chip links. The proposed design features a frequency-adaptive clock chain, a fast 16:1 clocked-CMOS multiplexer (C²MOS MUX) tree, and a full-rate synchronous current-mode logic (CML) clock driver. A prototype realized in 40-nm CMOS accomplishes a wide 0.1-to-11 Gb/s operation range (fmax/fmin = 110×). At 11 Gb/s, the prototype achieves 3.98 pJ/bit for a bit error rate (BER) < 10^-12 with a 60.9-ps eye width.

Original language	English
Title of host publication	2021 18th International SoC Design Conference (ISOCC)
Subtitle of host publication	Proceedings
Place of Publication	Danvers
Publisher	IEEE
Pages	41-42
Number of pages	2
ISBN (Electronic)	978-1-6654-0174-6
ISBN (Print)	978-1-6654-0175-3
DOIs	https://doi.org/10.1109/ISOCC53507.2021.9613887
Publication status	Published - 2021
Event	2021 18th International SoC Design Conference (ISOCC) - Hybrid at Jeju Island, Korea, Republic of Duration: 6 Oct 2021 → 9 Oct 2021 Conference number: 18tj

Publication series

Name	Proceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference	2021 18th International SoC Design Conference (ISOCC)
Abbreviated title	ISOCC 2021
Country/Territory	Korea, Republic of
City	Hybrid at Jeju Island
Period	6/10/21 → 9/10/21

Bibliographical note

Accepted author manuscript

Access to Document

10.1109/ISOCC53507.2021.9613887

JunFeng_ISOCC_WirelineTX_2Col2PageCameraReady_EmbeddedFontsAccepted author manuscript, 1.2 MB

Cite this

Feng, J., Beikmirza, M., Mehrpoo, M., de Vreede, L. C. N., & Alavi, M. S. (2021). A Versatile and Efficient 0.1-to-11 Gb/s CML Transmitter in 40-nm CMOS. In 2021 18th International SoC Design Conference (ISOCC): Proceedings (pp. 41-42). Article 9613887 (Proceedings - International SoC Design Conference 2021, ISOCC 2021). IEEE. https://doi.org/10.1109/ISOCC53507.2021.9613887

@inproceedings{ae5a01f8ffe148da8320715012210009,

title = "A Versatile and Efficient 0.1-to-11 Gb/s CML Transmitter in 40-nm CMOS",

abstract = "We present a wireline transmitter (TX) for re-configurable chip-to-chip links. The proposed design features a frequency-adaptive clock chain, a fast 16:1 clocked-CMOS multiplexer (C2MOS MUX) tree, and a full-rate synchronous current-mode logic (CML) clock driver. A prototype realized in 40-nm CMOS accomplishes a wide 0.1-to-11 Gb/s operation range (fmax/fmin = 110×). At 11 Gb/s, the prototype achieves 3.98 pJ/bit for a bit error rate (BER) < 10-12 with a 60.9-ps eye width.",

author = "Jun Feng and Mohammadreza Beikmirza and Mohammadreza Mehrpoo and {de Vreede}, {Leo C.N.} and Alavi, {Morteza S.}",

note = "Accepted author manuscript; 2021 18th International SoC Design Conference (ISOCC), ISOCC 2021 ; Conference date: 06-10-2021 Through 09-10-2021",

year = "2021",

doi = "10.1109/ISOCC53507.2021.9613887",

language = "English",

isbn = "978-1-6654-0175-3",

series = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

publisher = "IEEE",

pages = "41--42",

booktitle = "2021 18th International SoC Design Conference (ISOCC)",

address = "United States",

}

Feng, J, Beikmirza, M, Mehrpoo, M, de Vreede, LCN & Alavi, MS 2021, A Versatile and Efficient 0.1-to-11 Gb/s CML Transmitter in 40-nm CMOS. in 2021 18th International SoC Design Conference (ISOCC): Proceedings., 9613887, Proceedings - International SoC Design Conference 2021, ISOCC 2021, IEEE, Danvers, pp. 41-42, 2021 18th International SoC Design Conference (ISOCC), Hybrid at Jeju Island, Korea, Republic of, 6/10/21. https://doi.org/10.1109/ISOCC53507.2021.9613887

A Versatile and Efficient 0.1-to-11 Gb/s CML Transmitter in 40-nm CMOS. / Feng, Jun; Beikmirza, Mohammadreza ; Mehrpoo, Mohammadreza et al.
2021 18th International SoC Design Conference (ISOCC): Proceedings. Danvers: IEEE, 2021. p. 41-42 9613887 (Proceedings - International SoC Design Conference 2021, ISOCC 2021).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - A Versatile and Efficient 0.1-to-11 Gb/s CML Transmitter in 40-nm CMOS

AU - Feng, Jun

AU - Beikmirza, Mohammadreza

AU - Mehrpoo, Mohammadreza

AU - de Vreede, Leo C.N.

AU - Alavi, Morteza S.

N1 - Conference code: 18tj

PY - 2021

Y1 - 2021

N2 - We present a wireline transmitter (TX) for re-configurable chip-to-chip links. The proposed design features a frequency-adaptive clock chain, a fast 16:1 clocked-CMOS multiplexer (C2MOS MUX) tree, and a full-rate synchronous current-mode logic (CML) clock driver. A prototype realized in 40-nm CMOS accomplishes a wide 0.1-to-11 Gb/s operation range (fmax/fmin = 110×). At 11 Gb/s, the prototype achieves 3.98 pJ/bit for a bit error rate (BER) < 10-12 with a 60.9-ps eye width.

AB - We present a wireline transmitter (TX) for re-configurable chip-to-chip links. The proposed design features a frequency-adaptive clock chain, a fast 16:1 clocked-CMOS multiplexer (C2MOS MUX) tree, and a full-rate synchronous current-mode logic (CML) clock driver. A prototype realized in 40-nm CMOS accomplishes a wide 0.1-to-11 Gb/s operation range (fmax/fmin = 110×). At 11 Gb/s, the prototype achieves 3.98 pJ/bit for a bit error rate (BER) < 10-12 with a 60.9-ps eye width.

U2 - 10.1109/ISOCC53507.2021.9613887

DO - 10.1109/ISOCC53507.2021.9613887

M3 - Conference contribution

SN - 978-1-6654-0175-3

T3 - Proceedings - International SoC Design Conference 2021, ISOCC 2021

SP - 41

EP - 42

BT - 2021 18th International SoC Design Conference (ISOCC)

PB - IEEE

CY - Danvers

T2 - 2021 18th International SoC Design Conference (ISOCC)

Y2 - 6 October 2021 through 9 October 2021

ER -

A Versatile and Efficient 0.1-to-11 Gb/s CML Transmitter in 40-nm CMOS

Abstract

Publication series

Conference

Bibliographical note

Access to Document

Fingerprint

Cite this