A Wideband Linear Direct Digital RF Modulator using Harmonic Rejection and I/Q-Interleaving RF DACs

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

6 Citations (Scopus)

Abstract

This paper presents a wideband linear direct digital RF modulator (DDRM) in 40nm CMOS technology. It features an advanced 2nd-order-hold interpolation filter and I/Q-interleaving harmonic rejection RF DACs. The 2×9-bit DDRM core occupies 0.21mm2 and consumes only 110mW at 1 GHz. Within the 0.9-3.1GHz frequency range, the peak output power reaches +9.2dBm and the 3rd/5th harmonic rejection, C-IMD3, and OIP3 are respectively better than 30 dB, -44 dBc, and +25 dBm. The EVM and ACPR at 3 GHz for a 57-MHz 64-QAM signal are better than -30 dB and -45 dB, respectively, and ACPR remains as low as -44 dBc up to a wide bandwidth of 110 MHz.
Original languageEnglish
Title of host publication2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
Place of PublicationDanvers, MA
PublisherIEEE
Pages188 – 191
Number of pages4
ISBN (Electronic)978-1-5090-4626-3
DOIs
Publication statusPublished - 2017
EventRFIC 2017: IEEE Radio Frequency Integrated Circuits Symposium - Hawaii Convention Center, Honolulu, HI, United States
Duration: 4 Jun 20176 Jun 2017
http://rfic-ieee.org/

Conference

ConferenceRFIC 2017
CountryUnited States
CityHonolulu, HI
Period4/06/176/06/17
Internet address

Keywords

  • RF DAC
  • direct digital RF modulator
  • harmonic rejection
  • 2nd-order-hold
  • carrier aggregation
  • LTE

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