Abstract
Emerging non-volatile resistive RAM (RRAM) device technology has shown great potential to cultivate not only high-density memory storage, but also energy-efficient computing units. However, the unique challenges related to RRAM fabrication process render the traditional memory testing solutions inefficient and inadequate for high product quality. This paper presents low-cost design-for-testability (DFT) solutions that augment the testing process and improve the fault coverage. A computation-in-memory (CIM) based DFT is realized to expedite the detection and diagnosis of faults by developing logic designs involving multi-row activation. A novel addressing scheme is introduced to facilitate the diagnosis of faults. Reconfigurable logic designs are developed to detect unique RRAM faults that offer features such as programmable reference generations, period, and voltage of operation. DFT implementations are validated on a post-layout extracted platform and testing sequences are introduced by incorporating the proposed DFTs. Results show that more than 2.3× speedup and better coverage are achieved with 6× area reduction when compared with state-of-the-art solutions.
Original language | English |
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Title of host publication | Proceedings - 2022 IEEE International Test Conference, ITC 2022 |
Editors | Cristina Ceballos |
Place of Publication | Piscataway |
Publisher | IEEE |
Pages | 400-409 |
Number of pages | 10 |
ISBN (Electronic) | 978-1-6654-6270-9 |
ISBN (Print) | 978-1-6654-6271-6 |
DOIs | |
Publication status | Published - 2022 |
Event | 2022 IEEE International Test Conference (ITC) - Anaheim, United States Duration: 23 Sept 2022 → 30 Sept 2022 |
Publication series
Name | Proceedings - International Test Conference |
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Volume | 2022-September |
ISSN (Print) | 1089-3539 |
Conference
Conference | 2022 IEEE International Test Conference (ITC) |
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Country/Territory | United States |
City | Anaheim |
Period | 23/09/22 → 30/09/22 |
Bibliographical note
Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-careOtherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.
Keywords
- Design-for-testability (DFT)
- Testing RRAM
- computation-in-memory (CIM)
- binary logic
- RRAM defects