All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply

Chao Chieh Li, Min Shueh Yuan, Chia Chun Liao, Yu Tso Lin, Chih Hsien Chang, Robert Bogdan Staszewski

Research output: Contribution to journalArticleScientificpeer-review

13 Citations (Scopus)

Abstract

In this paper, we introduce an all-digital phase-locked loop (ADPLL) for Bluetooth low energy (BLE) that eliminates the need for a crystal oscillator (XO) other than a 32.768-kHz real-time clock (RTC) already present in wireless systems. Specifically, we propose to replace the conventional channel settling with a band settling that would be carried out only once per global device power up. The ADPLL locks to the center of the Bluetooth band (2440 MHz) upon system power-up and jointly performs an instantaneous channel hopping and Gaussian frequency shift keying (GFSK) modulation in a two-point manner to overcome the narrow PLL bandwidth (BW) due to the 32.768-kHz reference. Extensive calibrations linearize the effective cubic digitally controlled oscillator (DCO) transfer function to achieve a precise frequency range of hopping and modulation. Realized in 16-nm FinFET, it consumes <1 mW at ≤0.45 V, while achieving best-in-class performance and <100-ns hopping time.

Original languageEnglish
Article number8490904
Pages (from-to)3660-3671
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume53
Issue number12
DOIs
Publication statusPublished - 2018
Externally publishedYes

Keywords

  • All-digital phase-locked loop (ADPLL)
  • Bluetooth low energy (BLE)
  • channel hopping
  • digitally controlled oscillator (DCO)
  • FinFET
  • real-time clock (RTC)
  • voltage doubler

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