An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology

Dante Gabriel Muratore; Alper Akdikmen; Edoardo Bonizzoni; Franco Maloberti; U. Fat Chio; Sai Weng Sin; Rui Paulo Martins

doi:10.1109/ESSCIRC.2016.7598331

An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology

Dante Gabriel Muratore, Alper Akdikmen, Edoardo Bonizzoni, Franco Maloberti, U. Fat Chio, Sai Weng Sin, Rui Paulo Martins

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

8 Citations (Scopus)

3 Downloads (Pure)

Abstract

This paper presents the prototype of a single channel 8-bit 0.7-GS/s A/D converter implemented in a 65-nm CMOS process. The required thresholds are generated from the resistive interpolation embedded within the preamplifier preceding the latches. The active area of the chip is 150 × 220 μm² and the total power consumption is 5.96 mW. At Nyquist, the ADC achieves 6.62 ENOB, resulting in a figure of merit equal to 86.7 fJ/conversion-step.

Original language	English
Title of host publication	ESSCIRC 2016
Subtitle of host publication	42nd European Solid-State Circuits Conference
Publisher	IEEE
Pages	421-424
Number of pages	4
ISBN (Electronic)	9781509029723
DOIs	https://doi.org/10.1109/ESSCIRC.2016.7598331
Publication status	Published - 2016
Externally published	Yes
Event	42nd European Solid-State Circuits Conference, ESSCIRC 2016 - Lausanne, Switzerland Duration: 12 Sept 2016 → 15 Sept 2016

Publication series

Name	European Solid-State Circuits Conference
Volume	2016-October
ISSN (Print)	1930-8833

Conference

Conference	42nd European Solid-State Circuits Conference, ESSCIRC 2016
Country/Territory	Switzerland
City	Lausanne
Period	12/09/16 → 15/09/16

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10.1109/ESSCIRC.2016.7598331

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Muratore, D. G., Akdikmen, A., Bonizzoni, E., Maloberti, F., Chio, U. F., Sin, S. W., & Martins, R. P. (2016). An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology. In ESSCIRC 2016: 42nd European Solid-State Circuits Conference (pp. 421-424). Article 7598331 (European Solid-State Circuits Conference; Vol. 2016-October). IEEE. https://doi.org/10.1109/ESSCIRC.2016.7598331

@inproceedings{4bd82264f73c4ba18510160b7a2f2365,

title = "An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology",

abstract = "This paper presents the prototype of a single channel 8-bit 0.7-GS/s A/D converter implemented in a 65-nm CMOS process. The required thresholds are generated from the resistive interpolation embedded within the preamplifier preceding the latches. The active area of the chip is 150 × 220 μm2 and the total power consumption is 5.96 mW. At Nyquist, the ADC achieves 6.62 ENOB, resulting in a figure of merit equal to 86.7 fJ/conversion-step.",

author = "Muratore, {Dante Gabriel} and Alper Akdikmen and Edoardo Bonizzoni and Franco Maloberti and Chio, {U. Fat} and Sin, {Sai Weng} and Martins, {Rui Paulo}",

year = "2016",

doi = "10.1109/ESSCIRC.2016.7598331",

language = "English",

series = "European Solid-State Circuits Conference",

publisher = "IEEE",

pages = "421--424",

booktitle = "ESSCIRC 2016",

address = "United States",

note = "42nd European Solid-State Circuits Conference, ESSCIRC 2016 ; Conference date: 12-09-2016 Through 15-09-2016",

}

Muratore, DG, Akdikmen, A, Bonizzoni, E, Maloberti, F, Chio, UF, Sin, SW & Martins, RP 2016, An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology. in ESSCIRC 2016: 42nd European Solid-State Circuits Conference., 7598331, European Solid-State Circuits Conference, vol. 2016-October, IEEE, pp. 421-424, 42nd European Solid-State Circuits Conference, ESSCIRC 2016, Lausanne, Switzerland, 12/09/16. https://doi.org/10.1109/ESSCIRC.2016.7598331

An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology. / Muratore, Dante Gabriel; Akdikmen, Alper; Bonizzoni, Edoardo et al.
ESSCIRC 2016: 42nd European Solid-State Circuits Conference. IEEE, 2016. p. 421-424 7598331 (European Solid-State Circuits Conference; Vol. 2016-October).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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AU - Chio, U. Fat

AU - Sin, Sai Weng

AU - Martins, Rui Paulo

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AB - This paper presents the prototype of a single channel 8-bit 0.7-GS/s A/D converter implemented in a 65-nm CMOS process. The required thresholds are generated from the resistive interpolation embedded within the preamplifier preceding the latches. The active area of the chip is 150 × 220 μm2 and the total power consumption is 5.96 mW. At Nyquist, the ADC achieves 6.62 ENOB, resulting in a figure of merit equal to 86.7 fJ/conversion-step.

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An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology

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