An Asynchronous Pipelined Time-to-Digital Converter Using Time-Domain Subtraction

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Abstract

This paper presents the design of a low-power asynchronous pipelined time-to-digital converter (AP-TDC) to be employed in a time-domain signal processing system. The presented AP-TDC utilizes two novel concepts, namely time-domain subtraction and absolute value based algorithmic conversion. The design and
simulation of the AP-TDC is done using a standard CMOS 65 nm process. The least-significant-bit resolution of the AP-TDC is designed to be 200 ps and the AP-TDC outputs 7-bit digital words with an ENOB of 6.2 bits. The dynamic range of the TDC is 25.4 ns and the TDC core consumes 38 µW from a supply voltage of 1 V and has a total area of 1275 µm2. When compared to a Flash TDC implementation using the same delay elements, power consumption, total area, and conversion time are reduced by 28.3%, 31.5%, and 24.6%, respectively. The AP-TDC has a figure-of-merit of 9.9-fJ/conversion step.
Original languageEnglish
Title of host publicationProceedings of IEEE International Symposium on Circuits and Systems, ISCAS 2018
Place of PublicationPiscataway, NJ
PublisherIEEE
Pages1-5
Number of pages5
ISBN (Electronic)978-1-5386-4881-0
DOIs
Publication statusPublished - May 2018
EventISCAS 2018: IEEE International Symposium on Circuits and Systems - Florence, Italy
Duration: 27 May 201830 May 2018
http://www.iscas2018.org

Conference

ConferenceISCAS 2018
Abbreviated titleISCAS 2018
CountryItaly
CityFlorence
Period27/05/1830/05/18
Internet address

Keywords

  • asynchronous
  • time-to-digital converter
  • TDC
  • pipelined
  • absolute value based conversion
  • time subtraction
  • completion detection

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