An Automated and Process-Portable Generator for Phase-Locked Loop

Zhongkai Wang; Minsoo  Choi; Eric  Chang; John Wright; Wooham Bae; Sijun Du; Zhaokai  Liu; Nathan Narevsky; Colin Schmidt; Ayan  Biwas; Borivoje  Nikolic; Elad  Alon

doi:10.1109/DAC18074.2021.9586318

An Automated and Process-Portable Generator for Phase-Locked Loop

Zhongkai Wang, Minsoo Choi, Eric Chang, John Wright, Wooham Bae, Sijun Du, Zhaokai Liu, Nathan Narevsky, Colin Schmidt, Ayan Biwas, Borivoje Nikolic, Elad Alon

Electronic Instrumentation

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

2 Citations (Scopus)

Abstract

We present a bang-bang phase-locked loop (PLL) generator that encapsulates design methodologies for its circuit blocks and the complete PLL system. The generator is fully automated and parameterized, producing the layout and schematic based on process characterization and top-level specifications. Three 14GHz PLLs are instantiated in TSMC 16nm, GF 14nm and Intel 22nm technologies, demonstrating the process portability. The rapid generation time of less than four days enables fast PLL design and technology porting. The PLL design fabricated in TSMC 16nm shows RMS jitter of 565.4fs and power of 6.64mW from a 0.9V supply.

Original language	English
Title of host publication	2021 58th ACM/IEEE Design Automation Conference, DAC 2021
Subtitle of host publication	Proceedings
Place of Publication	Danvers
Publisher	IEEE
Pages	511-516
Number of pages	6
ISBN (Electronic)	978-1-6654-3274-0
ISBN (Print)	978-1-6654-3275-7
DOIs	https://doi.org/10.1109/DAC18074.2021.9586318
Publication status	Published - 2021
Event	2021 58th ACM/IEEE Design Automation Conference (DAC) - San Francisco, United States Duration: 5 Dec 2021 → 9 Dec 2021 Conference number: 58th

Publication series

Name	Proceedings - Design Automation Conference
Volume	2021-December
ISSN (Print)	0738-100X

Conference

Conference	2021 58th ACM/IEEE Design Automation Conference (DAC)
Abbreviated title	DAC 2021
Country/Territory	United States
City	San Francisco
Period	5/12/21 → 9/12/21

Keywords

Berkeley Analog Generator
jitter
phase noise
phase-locked loop
voltage-controlled oscillator

Access to Document

10.1109/DAC18074.2021.9586318

Cite this

Wang, Z., Choi, M., Chang, E., Wright, J., Bae, W., Du, S., Liu, Z., Narevsky, N., Schmidt, C., Biwas, A., Nikolic, B., & Alon, E. (2021). An Automated and Process-Portable Generator for Phase-Locked Loop. In 2021 58th ACM/IEEE Design Automation Conference, DAC 2021: Proceedings (pp. 511-516). Article 9586318 (Proceedings - Design Automation Conference; Vol. 2021-December). IEEE. https://doi.org/10.1109/DAC18074.2021.9586318

@inproceedings{f50ef25dda65451b80a87e030e4288a3,

title = "An Automated and Process-Portable Generator for Phase-Locked Loop",

abstract = "We present a bang-bang phase-locked loop (PLL) generator that encapsulates design methodologies for its circuit blocks and the complete PLL system. The generator is fully automated and parameterized, producing the layout and schematic based on process characterization and top-level specifications. Three 14GHz PLLs are instantiated in TSMC 16nm, GF 14nm and Intel 22nm technologies, demonstrating the process portability. The rapid generation time of less than four days enables fast PLL design and technology porting. The PLL design fabricated in TSMC 16nm shows RMS jitter of 565.4fs and power of 6.64mW from a 0.9V supply.",

keywords = "Berkeley Analog Generator, jitter, phase noise, phase-locked loop, voltage-controlled oscillator",

author = "Zhongkai Wang and Minsoo Choi and Eric Chang and John Wright and Wooham Bae and Sijun Du and Zhaokai Liu and Nathan Narevsky and Colin Schmidt and Ayan Biwas and Borivoje Nikolic and Elad Alon",

year = "2021",

doi = "10.1109/DAC18074.2021.9586318",

language = "English",

isbn = "978-1-6654-3275-7",

series = "Proceedings - Design Automation Conference",

publisher = "IEEE",

pages = "511--516",

booktitle = "2021 58th ACM/IEEE Design Automation Conference, DAC 2021",

address = "United States",

note = "2021 58th ACM/IEEE Design Automation Conference (DAC), DAC 2021 ; Conference date: 05-12-2021 Through 09-12-2021",

}

Wang, Z, Choi, M, Chang, E, Wright, J, Bae, W, Du, S, Liu, Z, Narevsky, N, Schmidt, C, Biwas, A, Nikolic, B & Alon, E 2021, An Automated and Process-Portable Generator for Phase-Locked Loop. in 2021 58th ACM/IEEE Design Automation Conference, DAC 2021: Proceedings., 9586318, Proceedings - Design Automation Conference, vol. 2021-December, IEEE, Danvers, pp. 511-516, 2021 58th ACM/IEEE Design Automation Conference (DAC), San Francisco, United States, 5/12/21. https://doi.org/10.1109/DAC18074.2021.9586318

An Automated and Process-Portable Generator for Phase-Locked Loop. / Wang, Zhongkai; Choi, Minsoo ; Chang, Eric et al.
2021 58th ACM/IEEE Design Automation Conference, DAC 2021: Proceedings. Danvers: IEEE, 2021. p. 511-516 9586318 (Proceedings - Design Automation Conference; Vol. 2021-December).

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

TY - GEN

T1 - An Automated and Process-Portable Generator for Phase-Locked Loop

AU - Wang, Zhongkai

AU - Choi, Minsoo

AU - Chang, Eric

AU - Wright, John

AU - Bae, Wooham

AU - Du, Sijun

AU - Liu, Zhaokai

AU - Narevsky, Nathan

AU - Schmidt, Colin

AU - Biwas, Ayan

AU - Nikolic, Borivoje

AU - Alon, Elad

N1 - Conference code: 58th

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N2 - We present a bang-bang phase-locked loop (PLL) generator that encapsulates design methodologies for its circuit blocks and the complete PLL system. The generator is fully automated and parameterized, producing the layout and schematic based on process characterization and top-level specifications. Three 14GHz PLLs are instantiated in TSMC 16nm, GF 14nm and Intel 22nm technologies, demonstrating the process portability. The rapid generation time of less than four days enables fast PLL design and technology porting. The PLL design fabricated in TSMC 16nm shows RMS jitter of 565.4fs and power of 6.64mW from a 0.9V supply.

AB - We present a bang-bang phase-locked loop (PLL) generator that encapsulates design methodologies for its circuit blocks and the complete PLL system. The generator is fully automated and parameterized, producing the layout and schematic based on process characterization and top-level specifications. Three 14GHz PLLs are instantiated in TSMC 16nm, GF 14nm and Intel 22nm technologies, demonstrating the process portability. The rapid generation time of less than four days enables fast PLL design and technology porting. The PLL design fabricated in TSMC 16nm shows RMS jitter of 565.4fs and power of 6.64mW from a 0.9V supply.

KW - Berkeley Analog Generator

KW - jitter

KW - phase noise

KW - phase-locked loop

KW - voltage-controlled oscillator

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DO - 10.1109/DAC18074.2021.9586318

M3 - Conference contribution

SN - 978-1-6654-3275-7

T3 - Proceedings - Design Automation Conference

SP - 511

EP - 516

BT - 2021 58th ACM/IEEE Design Automation Conference, DAC 2021

PB - IEEE

CY - Danvers

T2 - 2021 58th ACM/IEEE Design Automation Conference (DAC)

Y2 - 5 December 2021 through 9 December 2021

ER -

An Automated and Process-Portable Generator for Phase-Locked Loop

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Keywords

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