An Automated and Process-Portable Generator for Phase-Locked Loop

Zhongkai Wang, Minsoo Choi, Eric Chang, John Wright, Wooham Bae, Sijun Du, Zhaokai Liu, Nathan Narevsky, Colin Schmidt, Ayan Biwas, Borivoje Nikolic, Elad Alon

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Abstract

We present a bang-bang phase-locked loop (PLL) generator that encapsulates design methodologies for its circuit blocks and the complete PLL system. The generator is fully automated and parameterized, producing the layout and schematic based on process characterization and top-level specifications. Three 14GHz PLLs are instantiated in TSMC 16nm, GF 14nm and Intel 22nm technologies, demonstrating the process portability. The rapid generation time of less than four days enables fast PLL design and technology porting. The PLL design fabricated in TSMC 16nm shows RMS jitter of 565.4fs and power of 6.64mW from a 0.9V supply.
Original languageEnglish
Title of host publication2021 58th ACM/IEEE Design Automation Conference (DAC)
Subtitle of host publicationProceedings
Place of PublicationDanvers
PublisherIEEE
Pages511-516
Number of pages6
ISBN (Electronic)978-1-6654-3274-0
ISBN (Print)978-1-6654-3275-7
DOIs
Publication statusPublished - 2021
Event2021 58th ACM/IEEE Design Automation Conference (DAC) - San Francisco, United States
Duration: 5 Dec 20219 Dec 2021
Conference number: 58th

Conference

Conference2021 58th ACM/IEEE Design Automation Conference (DAC)
Abbreviated titleDAC 2021
CountryUnited States
CitySan Francisco
Period5/12/219/12/21

Keywords

  • phase-locked loop
  • Berkeley Analog Generator
  • phase noise
  • jitter
  • voltage-controlled oscillator

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