Point-of-care (PoC) diagnostics rely on the design of low-power and miniaturized readout units that can offer rapid and accurate test results, replacing the need for specialized equipment. CMOS technology can be exploited in order to design complex systems while achieving high energy efficiency for suitable operation in a mobile settings. This paper presents the design of a novel energy-efficient 4-channel wireless potentiostat chip, based on a dual-slope ADC architecture, that features a low-complexity wireless unit and a calibration approach that does not require additional circuitry. The chip was designed in a 0.35μm CMOS process. The simulated results suggest that each potentiostat channel can achieve an estimated energy efficiency of 2.5 pJ/bit from a 1.2 V supply.
|Title of host publication||2018 IEEE International Symposium on Circuits and Systems (ISCAS)|
|Number of pages||1|
|Publication status||Published - 2018|
|Event||ISCAS 2018: IEEE International Symposium on Circuits and Systems - Florence, Italy|
Duration: 27 May 2018 → 30 May 2018
|Abbreviated title||ISCAS 2018|
|Period||27/05/18 → 30/05/18|