An Intrinsically Linear Wideband Digital Polar PA Featuring AM-AM and AM-PM Corrections Through Nonlinear Sizing, Overdrive-Voltage Control, and Multiphase RF Clocking

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

5 Citations (Scopus)

Abstract

To fully benefit from the progress of CMOS technologies, it is desirable to completely digitize the TX, replacing its final stage with a digitally controlled PA (DPA). The DPA consists of arrays of small sub-PAs that are digitally controlled to modulate the output amplitude, thus operating as an RF-DAC [1-6]. DPAs are normally designed in a switched mode (Classes E/D/D-1, etc.) to achieve high efficiency while using high sampling rate to attenuate and push the spectral images to higher frequencies. However, they suffer from high nonlinearity in their AM-code-word (ACW) to AM and ACW-to-PM conversion. To correct for such nonlinearities, digital pre-distortion (DPD) of the input signal is often used [1-3], typically implemented by look-up tables (LUT). Unfortunately, DPD approaches suffer from large signal-BW expansion due to their inherently nonlinear characteristics. This, combined with the already present BW regrowth in a polar TX in the AM and PM paths, yields significant hardware-speed/power constraints when the signal BW becomes large. For a Cartesian TX, the use of LUT-DPD is even more complicated since a full 2D LUT is typically required [2]. To relax the overall system complexity, it is highly desirable to have a PA with a maximum inherent linearity without compromising its power or efficiency. In this work, an ACW-AM correction based on nonlinear sizing along with controlling the peak voltage of RF clocks (overdrive voltage tuning) and a ACW-PM correction based on multiphase RF clocking are introduced to linearize the characteristic curves of a Class-E polar DPA with intent to avoid any kind of pre-distortion.
Original languageEnglish
Title of host publication2017 IEEE International Solid-State Circuits Conference (ISSCC)
Subtitle of host publicationDigest of Technical Papers
EditorsLaura C. Fujino
Place of PublicationDanvers, MA
PublisherIEEE
Pages300-301
Number of pages2
ISBN (Electronic)978-1-5090-3758-2
ISBN (Print)978-1-5090-3757-5
DOIs
Publication statusPublished - 2017
EventISSCC 2017: 64th IEEE International Solid-State Circuits Conference - San Francisco, CA, United States
Duration: 5 Feb 20179 Feb 2017

Conference

ConferenceISSCC 2017
CountryUnited States
CitySan Francisco, CA
Period5/02/179/02/17

Keywords

  • Radio frequency
  • Power amplifiers
  • Linearity
  • Tuning
  • Delays
  • Wideband

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