An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order ΔΣ Loop

Peng Chen, Xiongchuan Huang, Yue Chen, Lianbo Wu, Robert Bogdan Staszewski

Research output: Contribution to journalArticleScientificpeer-review

2 Citations (Scopus)
80 Downloads (Pure)

Abstract

To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order ΔΣ time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A system self-calibration algorithm is proposed to calibrate nonlinearities of the analog circuitry. The operation is robust over PVT variations since the delay information is normalized to the input clock period. To verify the proposed idea, two different digital-to-time converters performing the on-chip delay are measured and analyzed at 50-MHz clocking frequency with 0.65-ps standard time deviation per measurement.

Original languageEnglish
Pages (from-to)3734-3744
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume65
Issue number11
DOIs
Publication statusPublished - 2018

Keywords

  • buit-in selft-test (BIST)
  • Calibration
  • Charge pumps
  • Clocks
  • Delays
  • Digital-to-time converter (DTC)
  • first-order delta-sigma modulator
  • Linearity
  • noise shaping
  • PLL
  • self calibration
  • System-on-chip
  • time-to-digital converter (TDC)

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