An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS

Zhongkai Wang, Minsoo Choi, Kyoungtae Lee, Kwanseo Park, Zhaokai Liu, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon

Research output: Contribution to journalArticleScientificpeer-review

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Abstract

This article presents a 200-Gb/s pulse amplitude-modulation four-level (PAM-4) and 100-Gb/s non-return-to-zero (NRZ) transmitter (TX) in 28-nm CMOS technology. To achieve the target data rate, the output bandwidth and swing of the proposed TX are optimized by minimizing the output capacitance of the 4:1 multiplexer (MUX) and driver stage with pull-up current sources and adopting a fully reconfigurable 5-tap feed-forward equalizer (FFE). The key circuit includes a segmented 8:4 MUX and 4:1 MUX/driver, a thermal encoder and retimer, and a flexible clock distribution network. Using the layout generated with Berkeley Analog Generator (BAG), the proposed TX achieves an eye opening with >52.9-mV eye height, 0.36 UI eye width, >98% RLM, and 4.63 pJ/b at 200-Gb/s PAM-4 signaling under >6-dB channel loss at 50 GHz, demonstrating the highest data rate achieved using a planar process.

Original languageEnglish
Pages (from-to)21-31
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume57
Issue number1
DOIs
Publication statusPublished - 2022

Keywords

  • 28 nm
  • 4:1 multiplexer (MUX)
  • Berkeley Analog Generator (BAG)
  • clock distribution
  • four-level pulse-amplitude modulation (PAM-4)
  • pulse generator
  • quarter-rate
  • SerDes
  • transmitter (TX)
  • wireline

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