TY - JOUR
T1 - An Ultra-Low Power 1.7-2.7 GHz Fractional-N Sub-Sampling Digital Frequency Synthesizer and Modulator for IoT Applications in 40 nm CMOS
AU - Liu, Yao-Hong
AU - Van Den Heuvel, Johan
AU - Kuramochi, Takashi
AU - Busze, Benjamin
AU - Mateman, Paul
AU - Chillara, Vamshi Krishna
AU - Wang, Bindi
AU - Staszewski, Robert Bogdan
AU - Philips, Kathleen
PY - 2017
Y1 - 2017
N2 - This paper introduces an ultra-low power 1.7-2.7-GHz fractional-N sub-sampling digital PLL (SS-DPLL) for Internet-of-Things (IoT) applications targeting compliance with Bluetooth Low Energy (BLE) and IEEE802.15.4 standards. A snapshot time-to-digital converter (TDC) acts as a digital sub-sampler featuring an increased out-of-range gain and without any assistance from the traditional counting of DCO edges, thus further reducing power consumption. With a proposed DCO-divider phase rotation in the feedback path, the impact of the digital-to-time converter's (DTC's) non-linearity on the PLL is reduced and improves fractional spurs by at least 8 dB across BLE channels. Moreover, a “variable-preconditioned LMS” calibration algorithm is introduced to dynamically correct the DTC gain error with fractional frequency control word (FCW) down to 1/16384. Fabricated in 40 nm CMOS, the SS-DPLL achieves phase noise performance of -109 dBc/Hz at 1 MHz offset, while consuming a record-low power of 1.19 mW.
AB - This paper introduces an ultra-low power 1.7-2.7-GHz fractional-N sub-sampling digital PLL (SS-DPLL) for Internet-of-Things (IoT) applications targeting compliance with Bluetooth Low Energy (BLE) and IEEE802.15.4 standards. A snapshot time-to-digital converter (TDC) acts as a digital sub-sampler featuring an increased out-of-range gain and without any assistance from the traditional counting of DCO edges, thus further reducing power consumption. With a proposed DCO-divider phase rotation in the feedback path, the impact of the digital-to-time converter's (DTC's) non-linearity on the PLL is reduced and improves fractional spurs by at least 8 dB across BLE channels. Moreover, a “variable-preconditioned LMS” calibration algorithm is introduced to dynamically correct the DTC gain error with fractional frequency control word (FCW) down to 1/16384. Fabricated in 40 nm CMOS, the SS-DPLL achieves phase noise performance of -109 dBc/Hz at 1 MHz offset, while consuming a record-low power of 1.19 mW.
KW - LMS
KW - All-digital PLL
KW - digital-to-time converter
KW - fractional-N PLL
KW - low-power transceiver
KW - sub-sampling PLL
KW - time-to-digital converter
KW - Internet of Things
U2 - 10.1109/tcsi.2016.2625462
DO - 10.1109/tcsi.2016.2625462
M3 - Article
SN - 1549-8328
VL - 64
SP - 1094
EP - 1105
JO - IEEE Transactions on Circuits and Systems Part 1: Regular Papers
JF - IEEE Transactions on Circuits and Systems Part 1: Regular Papers
IS - 5
ER -