Analysis and design of bias circuits tolerating output voltages above BV-CEO

H Veenstra, GAM Hurkx, D van Goor, H Brekelmans, JR Long

Research output: Contribution to journal › Article › Scientific › peer-review

Original language	Undefined/Unknown
Pages (from-to)	2008-2018
Number of pages	11
Journal	IEEE Journal of Solid State Circuits
Volume	40
Issue number	10
Publication status	Published - 2005

Keywords

@article{d645a36bd1274ffca17c13446d524036,

title = "Analysis and design of bias circuits tolerating output voltages above BV-CEO",

keywords = "academic journal papers, ZX CWTS 1.00 <= JFIS < 3.00",

author = "H Veenstra and GAM Hurkx and {van Goor}, D and H Brekelmans and JR Long",

year = "2005",

language = "Undefined/Unknown",

volume = "40",

pages = "2008--2018",

journal = "IEEE Journal of Solid State Circuits",

issn = "0018-9200",

publisher = "IEEE",

number = "10",

}

TY - JOUR

T1 - Analysis and design of bias circuits tolerating output voltages above BV-CEO

AU - Veenstra, H

AU - Hurkx, GAM

AU - van Goor, D

AU - Brekelmans, H

AU - Long, JR

PY - 2005

Y1 - 2005

KW - academic journal papers

KW - ZX CWTS 1.00 <= JFIS < 3.00

M3 - Article

SN - 0018-9200

VL - 40

SP - 2008

EP - 2018

JO - IEEE Journal of Solid State Circuits

JF - IEEE Journal of Solid State Circuits

IS - 10

ER -