TY - JOUR
T1 - APmap
T2 - An Open-Source Compiler for Automata Processors
AU - Yu, Jintao
AU - Lebdeh, Muath Abu
AU - Du Nguyen, Hoang Anh
AU - Taouil, Mottaqiallah
AU - Hamdioui, Said
PY - 2021
Y1 - 2021
N2 - A novel type of hardware accelerators called automata processors (APs) have been proposed to accelerate finite-state automata. The bone structure of an AP is a hierarchical routing matrix that connects many memory arrays. With this structure, an AP can process an input symbol every clock cycle, and hence achieve much higher performance compared to conventional architectures. However, the design automation for the APs is not well researched. This article proposes a fully automated tool named APmap for mapping the automata to APs that use a two-level routing matrix. APmap first partitions a large automaton into small graphs and then maps them. Multiple transformations are applied to the automaton by APmap to meet hardware constraints. The experiments on a standard benchmark suite show that our approach leads to around 19% less storage utilization compared to state-of-the-art.
AB - A novel type of hardware accelerators called automata processors (APs) have been proposed to accelerate finite-state automata. The bone structure of an AP is a hierarchical routing matrix that connects many memory arrays. With this structure, an AP can process an input symbol every clock cycle, and hence achieve much higher performance compared to conventional architectures. However, the design automation for the APs is not well researched. This article proposes a fully automated tool named APmap for mapping the automata to APs that use a two-level routing matrix. APmap first partitions a large automaton into small graphs and then maps them. Multiple transformations are applied to the automaton by APmap to meet hardware constraints. The experiments on a standard benchmark suite show that our approach leads to around 19% less storage utilization compared to state-of-the-art.
KW - Automata Processor
KW - design automation
KW - mapping
KW - graph partitioning
UR - http://www.scopus.com/inward/record.url?scp=85101845575&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2021.3062328
DO - 10.1109/TCAD.2021.3062328
M3 - Article
AN - SCOPUS:85101845575
SN - 0278-0070
VL - 41
SP - 196
EP - 200
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 1
ER -